mirror of
https://github.com/RPCS3/llvm.git
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Check in conditional branches for constant islands. Still need to finish
conditional branches for very large targets. That will be the next small patch. Everything now should in principle work as good (functionality wise) as without constant islands so we decided at Mips/Imagination to make constant islands the default for Mips16 now so that it will get excercised a lot and this port is still experimentatl though hopefully soon we will change the status. Some more cleanup and code review is in order but things are converging fast. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195902 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Reed Kotler
parent
92b8543819
commit
18a777a09a
@ -77,6 +77,103 @@ static cl::opt<bool> NoLoadRelaxation(
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cl::desc("Don't relax loads to long loads - for testing purposes"),
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cl::Hidden);
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static unsigned int branchTargetOperand(MachineInstr *MI) {
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switch (MI->getOpcode()) {
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case Mips::Bimm16:
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case Mips::BimmX16:
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case Mips::Bteqz16:
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case Mips::BteqzX16:
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case Mips::Btnez16:
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case Mips::BtnezX16:
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case Mips::Jal16:
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return 0;
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case Mips::BeqzRxImm16:
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case Mips::BeqzRxImmX16:
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case Mips::BnezRxImm16:
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case Mips::BnezRxImmX16:
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return 1;
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}
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llvm_unreachable("Unknown branch type");
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}
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static unsigned int longformBranchOpcode(unsigned int Opcode) {
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switch (Opcode) {
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case Mips::Bimm16:
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case Mips::BimmX16:
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return Mips::BimmX16;
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case Mips::Bteqz16:
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case Mips::BteqzX16:
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return Mips::BteqzX16;
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case Mips::Btnez16:
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case Mips::BtnezX16:
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return Mips::BtnezX16;
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case Mips::Jal16:
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return Mips::Jal16;
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case Mips::BeqzRxImm16:
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case Mips::BeqzRxImmX16:
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return Mips::BeqzRxImmX16;
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case Mips::BnezRxImm16:
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case Mips::BnezRxImmX16:
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return Mips::BnezRxImmX16;
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}
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llvm_unreachable("Unknown branch type");
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}
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//
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// FIXME: need to go through this whole constant islands port and check the math
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// for branch ranges and clean this up and make some functions to calculate things
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// that are done many times identically.
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// Need to refactor some of the code to call this routine.
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//
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static unsigned int branchMaxOffsets(unsigned int Opcode) {
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unsigned Bits, Scale;
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switch (Opcode) {
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case Mips::Bimm16:
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Bits = 11;
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Scale = 2;
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break;
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case Mips::BimmX16:
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Bits = 16;
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Scale = 2;
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break;
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case Mips::BeqzRxImm16:
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Bits = 8;
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Scale = 2;
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break;
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case Mips::BeqzRxImmX16:
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Bits = 16;
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Scale = 2;
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break;
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case Mips::BnezRxImm16:
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Bits = 8;
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Scale = 2;
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break;
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case Mips::BnezRxImmX16:
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Bits = 16;
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Scale = 2;
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break;
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case Mips::Bteqz16:
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Bits = 8;
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Scale = 2;
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break;
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case Mips::BteqzX16:
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Bits = 16;
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Scale = 2;
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break;
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case Mips::Btnez16:
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Bits = 8;
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Scale = 2;
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break;
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case Mips::BtnezX16:
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Bits = 16;
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Scale = 2;
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break;
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default:
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llvm_unreachable("Unknown branch type");
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}
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unsigned MaxOffs = ((1 << (Bits-1))-1) * Scale;
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return MaxOffs;
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}
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namespace {
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@ -603,6 +700,47 @@ initializeFunctionInfo(const std::vector<MachineInstr*> &CPEMIs) {
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Bits = 16;
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Scale = 2;
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isCond = false;
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break;
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case Mips::BeqzRxImm16:
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Bits = 8;
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Scale = 2;
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isCond = true;
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break;
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case Mips::BeqzRxImmX16:
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Bits = 16;
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Scale = 2;
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isCond = true;
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break;
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case Mips::BnezRxImm16:
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Bits = 8;
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Scale = 2;
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isCond = true;
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break;
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case Mips::BnezRxImmX16:
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Bits = 16;
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Scale = 2;
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isCond = true;
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break;
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case Mips::Bteqz16:
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Bits = 8;
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Scale = 2;
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isCond = true;
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break;
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case Mips::BteqzX16:
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Bits = 16;
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Scale = 2;
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isCond = true;
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break;
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case Mips::Btnez16:
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Bits = 8;
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Scale = 2;
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isCond = true;
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break;
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case Mips::BtnezX16:
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Bits = 16;
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Scale = 2;
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isCond = true;
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break;
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}
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// Record this immediate branch.
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unsigned MaxOffs = ((1 << (Bits-1))-1) * Scale;
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@ -1382,7 +1520,8 @@ unsigned PCAdj = 4;
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/// away to fit in its displacement field.
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bool MipsConstantIslands::fixupImmediateBr(ImmBranch &Br) {
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MachineInstr *MI = Br.MI;
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MachineBasicBlock *DestBB = MI->getOperand(0).getMBB();
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unsigned TargetOperand = branchTargetOperand(MI);
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MachineBasicBlock *DestBB = MI->getOperand(TargetOperand).getMBB();
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// Check to see if the DestBB is already in-range.
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if (isBBInRange(MI, DestBB, Br.MaxDisp))
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@ -1434,13 +1573,26 @@ MipsConstantIslands::fixupUnconditionalBr(ImmBranch &Br) {
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return true;
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}
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/// fixupConditionalBr - Fix up a conditional branch whose destination is too
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/// far away to fit in its displacement field. It is converted to an inverse
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/// conditional branch + an unconditional branch to the destination.
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bool
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MipsConstantIslands::fixupConditionalBr(ImmBranch &Br) {
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MachineInstr *MI = Br.MI;
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MachineBasicBlock *DestBB = MI->getOperand(0).getMBB();
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unsigned TargetOperand = branchTargetOperand(MI);
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MachineBasicBlock *DestBB = MI->getOperand(TargetOperand).getMBB();
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unsigned Opcode = MI->getOpcode();
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unsigned LongFormOpcode = longformBranchOpcode(Opcode);
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unsigned LongFormMaxOff = branchMaxOffsets(LongFormOpcode);
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// Check to see if the DestBB is already in-range.
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if (isBBInRange(MI, DestBB, LongFormMaxOff)) {
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Br.MaxDisp = LongFormMaxOff;
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MI->setDesc(TII->get(LongFormOpcode));
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return true;
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}
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llvm_unreachable("Fixup of very long conditional branch not working yet.");
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// Add an unconditional branch to the destination and invert the branch
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// condition to jump over it:
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@ -55,9 +55,9 @@ Mips16HardFloat("mips16-hard-float", cl::NotHidden,
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static cl::opt<bool>
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Mips16ConstantIslands(
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"mips16-constant-islands", cl::Hidden,
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cl::desc("MIPS: mips16 constant islands enable. experimental feature"),
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cl::init(false));
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"mips16-constant-islands", cl::NotHidden,
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cl::desc("MIPS: mips16 constant islands enable."),
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cl::init(true));
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void MipsSubtarget::anchor() { }
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@ -1,4 +1,4 @@
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; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
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; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=pic -mips16-constant-islands=false -O3 < %s | FileCheck %s -check-prefix=16
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@.str = private unnamed_addr constant [4 x i8] c"%i\0A\00", align 1
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@ -1,6 +1,6 @@
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; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=1
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; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=static -mips16-constant-islands=false < %s | FileCheck %s -check-prefix=1
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; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=ci
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; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=pic < %s | FileCheck %s -check-prefix=ci
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@i = common global i32 0, align 4
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@j = common global i32 0, align 4
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133
test/CodeGen/Mips/lcb2.ll
Normal file
133
test/CodeGen/Mips/lcb2.ll
Normal file
@ -0,0 +1,133 @@
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; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=static -mips16-constant-islands=true < %s | FileCheck %s -check-prefix=lcb
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; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=static -mips16-constant-islands=true < %s | FileCheck %s -check-prefix=lcbn
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@i = global i32 0, align 4
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@j = common global i32 0, align 4
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@k = common global i32 0, align 4
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; Function Attrs: nounwind optsize
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define i32 @bnez() #0 {
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entry:
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%0 = load i32* @i, align 4, !tbaa !1
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%cmp = icmp eq i32 %0, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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tail call void asm sideeffect ".space 10000", ""() #1, !srcloc !5
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store i32 0, i32* @i, align 4, !tbaa !1
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br label %if.end
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if.end: ; preds = %if.then, %entry
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ret i32 0
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}
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; lcb: .ent bnez
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; lcbn: .ent bnez
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; lcb: bnez ${{[0-9]+}}, $BB{{[0-9]+}}_{{[0-9]+}}
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; lcbn-NOT: bnez ${{[0-9]+}}, $BB{{[0-9]+}}_{{[0-9]+}} # 16 bit inst
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; lcb: .end bnez
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; lcbn: .end bnez
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; Function Attrs: nounwind optsize
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define i32 @beqz() #0 {
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entry:
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%0 = load i32* @i, align 4, !tbaa !1
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%cmp = icmp eq i32 %0, 0
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br i1 %cmp, label %if.then, label %if.else
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if.then: ; preds = %entry
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store i32 10, i32* @j, align 4, !tbaa !1
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tail call void asm sideeffect ".space 10000", ""() #1, !srcloc !6
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br label %if.end
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if.else: ; preds = %entry
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store i32 55, i32* @j, align 4, !tbaa !1
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tail call void asm sideeffect ".space 10000", ""() #1, !srcloc !7
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br label %if.end
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if.end: ; preds = %if.else, %if.then
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ret i32 0
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}
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; lcb: .ent beqz
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; lcbn: .ent beqz
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; lcb: beqz ${{[0-9]+}}, $BB{{[0-9]+}}_{{[0-9]+}}
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; lcbn-NOT: beqz ${{[0-9]+}}, $BB{{[0-9]+}}_{{[0-9]+}} # 16 bit inst
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; lcb: .end beqz
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; lcbn: .end beqz
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; Function Attrs: nounwind optsize
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define void @bteqz() #0 {
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entry:
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%0 = load i32* @i, align 4, !tbaa !1
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%1 = load i32* @j, align 4, !tbaa !1
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%cmp = icmp eq i32 %0, %1
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br i1 %cmp, label %if.then, label %if.else
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if.then: ; preds = %entry
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store i32 1, i32* @k, align 4, !tbaa !1
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tail call void asm sideeffect ".space 1000", ""() #1, !srcloc !8
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br label %if.end
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if.else: ; preds = %entry
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tail call void asm sideeffect ".space 1000", ""() #1, !srcloc !9
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store i32 2, i32* @k, align 4, !tbaa !1
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br label %if.end
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if.end: ; preds = %if.else, %if.then
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ret void
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}
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; lcb: .ent bteqz
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; lcbn: .ent bteqz
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; lcb: btnez $BB{{[0-9]+}}_{{[0-9]+}}
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; lcbn-NOT: btnez $BB{{[0-9]+}}_{{[0-9]+}} # 16 bit inst
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; lcb: .end bteqz
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; lcbn: .end bteqz
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; Function Attrs: nounwind optsize
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define void @btz() #0 {
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entry:
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%0 = load i32* @i, align 4, !tbaa !1
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%1 = load i32* @j, align 4, !tbaa !1
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%cmp1 = icmp sgt i32 %0, %1
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br i1 %cmp1, label %if.then, label %if.end
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if.then: ; preds = %entry, %if.then
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tail call void asm sideeffect ".space 60000", ""() #1, !srcloc !10
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%2 = load i32* @i, align 4, !tbaa !1
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%3 = load i32* @j, align 4, !tbaa !1
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%cmp = icmp sgt i32 %2, %3
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br i1 %cmp, label %if.then, label %if.end
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if.end: ; preds = %if.then, %entry
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ret void
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}
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; lcb: .ent btz
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; lcbn: .ent btz
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; lcb: bteqz $BB{{[0-9]+}}_{{[0-9]+}}
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; lcbn-NOT: bteqz $BB{{[0-9]+}}_{{[0-9]+}} # 16 bit inst
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; lcb: btnez $BB{{[0-9]+}}_{{[0-9]+}}
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; lcbn-NOT: btnez $BB{{[0-9]+}}_{{[0-9]+}} # 16 bit inst
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; lcb: .end btz
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; lcbn: .end btz
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attributes #0 = { nounwind optsize "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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attributes #1 = { nounwind }
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!llvm.ident = !{!0}
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!0 = metadata !{metadata !"clang version 3.5 (gitosis@dmz-portal.mips.com:clang.git ed197d08c90d82e1119774e10920e6f7a841c8ec) (gitosis@dmz-portal.mips.com:llvm.git b9235a363fa2dddb26ac01cbaed58efbc9eff392)"}
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!1 = metadata !{metadata !2, metadata !2, i64 0}
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!2 = metadata !{metadata !"int", metadata !3, i64 0}
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!3 = metadata !{metadata !"omnipotent char", metadata !4, i64 0}
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!4 = metadata !{metadata !"Simple C/C++ TBAA"}
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!5 = metadata !{i32 59}
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!6 = metadata !{i32 156}
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!7 = metadata !{i32 210}
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!8 = metadata !{i32 299}
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!9 = metadata !{i32 340}
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!10 = metadata !{i32 412}
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