RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2024-11-25 04:39:51 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Don't feed 19 bit immediates to ILA.

Browse Source 
Patch (slightly modified) by Visa Putkinen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122052 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kalle Raiskila 2010-12-17 09:36:09 +00:00
parent 127a6a47bd
commit 18aa393153
2 changed files with 16 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
lib/Target/CellSPU/SPUOperands.td
View File

@ -143,7 +143,7 @@ def immU16 : PatLeaf<(imm), [{
def imm18 : PatLeaf<(imm), [{
// imm18 predicate: True if the immediate fits into an 18-bit unsigned field.
int Value = (int) N->getZExtValue();
return ((Value & ((1 << 19) - 1)) == Value);
return isUInt<18>(Value);
}]>;
def lo16 : PatLeaf<(imm), [{
@ -203,7 +203,7 @@ def FPimm_sext16 : SDNodeXForm<fpimm, [{
def FPimm_u18 : SDNodeXForm<fpimm, [{
float fval = N->getValueAPF().convertToFloat();
return getI32Imm(FloatToBits(fval) & ((1 << 19) - 1));
return getI32Imm(FloatToBits(fval) & ((1 << 18) - 1));
}]>;
def fpimmSExt16 : PatLeaf<(fpimm), [{
@ -225,7 +225,7 @@ def hi16_f32 : PatLeaf<(fpimm), [{
def fpimm18 : PatLeaf<(fpimm), [{
if (N->getValueType(0) == MVT::f32) {
uint32_t Value = FloatToBits(N->getValueAPF().convertToFloat());
return ((Value & ((1 << 19) - 1)) == Value);
return isUInt<18>(Value);
}
return false;

15
test/CodeGen/CellSPU/immed32.ll
View File

@ -1,6 +1,6 @@
; RUN: llc < %s -march=cellspu > %t1.s
; RUN: grep ilhu %t1.s | count 8
; RUN: grep iohl %t1.s | count 6
; RUN: grep ilhu %t1.s | count 9
; RUN: grep iohl %t1.s | count 7
; RUN: grep -w il %t1.s | count 3
; RUN: grep 16429 %t1.s | count 1
; RUN: grep 63572 %t1.s | count 1
@ -12,6 +12,7 @@
; RUN: grep 49077 %t1.s | count 1
; RUN: grep 1267 %t1.s | count 2
; RUN: grep 16309 %t1.s | count 1
; RUN: cat %t1.s | FileCheck %s
target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
target triple = "spu"
@ -31,6 +32,16 @@ define i32 @test_4() {
ret i32 -512 ;; IL via pattern
}
define i32 @test_5()
{
;CHECK: test_5:
;CHECK-NOT: ila $3, 40000
;CHECK: ilhu
;CHECK: iohl
;CHECK: bi $lr
ret i32 400000
}
;; double float floatval
;; 0x4005bf0a80000000 0x402d|f854 2.718282
define float @float_const_1() {