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This patch adds a predicate to existing mips32 and mips64 so that those
instruction encodings can be excluded during mips16 processing.
This revision fixes the issue raised by Jim Grosbach.
bool hasStandardEncoding() const { return !inMips16Mode(); }
When micromips is added it will be
bool StandardEncoding() const { return !inMips16Mode()&& !inMicroMipsMode(); }
No additional testing is needed other than to assure that there is no regression
from this patch.
Patch by Reed Kotler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157234 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
parent
a7a2a3635f
commit
18f3c78092
@ -49,21 +49,24 @@ class Div64<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
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Div<op, func, instr_asm, itin, CPU64Regs, [HI64, LO64]>;
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multiclass Atomic2Ops64<PatFrag Op, string Opstr> {
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def #NAME# : Atomic2Ops<Op, Opstr, CPU64Regs, CPURegs>, Requires<[NotN64]>;
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def _P8 : Atomic2Ops<Op, Opstr, CPU64Regs, CPU64Regs>, Requires<[IsN64]> {
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def #NAME# : Atomic2Ops<Op, Opstr, CPU64Regs, CPURegs>,
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Requires<[NotN64, HasStandardEncoding]>;
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def _P8 : Atomic2Ops<Op, Opstr, CPU64Regs, CPU64Regs>,
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Requires<[IsN64, HasStandardEncoding]> {
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let isCodeGenOnly = 1;
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}
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}
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multiclass AtomicCmpSwap64<PatFrag Op, string Width> {
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def #NAME# : AtomicCmpSwap<Op, Width, CPU64Regs, CPURegs>, Requires<[NotN64]>;
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def #NAME# : AtomicCmpSwap<Op, Width, CPU64Regs, CPURegs>,
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Requires<[NotN64, HasStandardEncoding]>;
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def _P8 : AtomicCmpSwap<Op, Width, CPU64Regs, CPU64Regs>,
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Requires<[IsN64]> {
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Requires<[IsN64, HasStandardEncoding]> {
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let isCodeGenOnly = 1;
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}
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}
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}
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let usesCustomInserter = 1, Predicates = [HasMips64],
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let usesCustomInserter = 1, Predicates = [HasMips64, HasStandardEncoding],
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DecoderNamespace = "Mips64" in {
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defm ATOMIC_LOAD_ADD_I64 : Atomic2Ops64<atomic_load_add_64, "load_add_64">;
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defm ATOMIC_LOAD_SUB_I64 : Atomic2Ops64<atomic_load_sub_64, "load_sub_64">;
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@ -108,7 +111,8 @@ def DSRLV : shift_rotate_reg<0x16, 0x00, "dsrlv", srl, CPU64Regs>;
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def DSRAV : shift_rotate_reg<0x17, 0x00, "dsrav", sra, CPU64Regs>;
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}
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// Rotate Instructions
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let Predicates = [HasMips64r2], DecoderNamespace = "Mips64" in {
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let Predicates = [HasMips64r2, HasStandardEncoding],
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DecoderNamespace = "Mips64" in {
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def DROTR : shift_rotate_imm64<0x3a, 0x01, "drotr", rotr>;
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def DROTRV : shift_rotate_reg<0x16, 0x01, "drotrv", rotr, CPU64Regs>;
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}
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@ -138,12 +142,16 @@ defm ULD : LoadM64<0x37, "uld", load_u, 1>;
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defm USD : StoreM64<0x3f, "usd", store_u, 1>;
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/// Load-linked, Store-conditional
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def LLD : LLBase<0x34, "lld", CPU64Regs, mem>, Requires<[NotN64]>;
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def LLD_P8 : LLBase<0x34, "lld", CPU64Regs, mem64>, Requires<[IsN64]> {
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def LLD : LLBase<0x34, "lld", CPU64Regs, mem>,
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Requires<[NotN64, HasStandardEncoding]>;
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def LLD_P8 : LLBase<0x34, "lld", CPU64Regs, mem64>,
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Requires<[IsN64, HasStandardEncoding]> {
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let isCodeGenOnly = 1;
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}
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def SCD : SCBase<0x3c, "scd", CPU64Regs, mem>, Requires<[NotN64]>;
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def SCD_P8 : SCBase<0x3c, "scd", CPU64Regs, mem64>, Requires<[IsN64]> {
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def SCD : SCBase<0x3c, "scd", CPU64Regs, mem>,
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Requires<[NotN64, HasStandardEncoding]>;
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def SCD_P8 : SCBase<0x3c, "scd", CPU64Regs, mem64>,
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Requires<[IsN64, HasStandardEncoding]> {
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let isCodeGenOnly = 1;
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}
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@ -187,7 +195,7 @@ def LEA_ADDiu64 : EffectiveAddress<"daddiu\t$rt, $addr", CPU64Regs, mem_ea_64>;
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}
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let Uses = [SP_64], DecoderNamespace = "Mips64" in
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def DynAlloc64 : EffectiveAddress<"daddiu\t$rt, $addr", CPU64Regs, mem_ea_64>,
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Requires<[IsN64]> {
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Requires<[IsN64, HasStandardEncoding]> {
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let isCodeGenOnly = 1;
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}
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let DecoderNamespace = "Mips64" in {
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@ -209,7 +217,7 @@ def SLL64_64 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt),
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//===----------------------------------------------------------------------===//
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// extended loads
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let Predicates = [NotN64] in {
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let Predicates = [NotN64, HasStandardEncoding] in {
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def : Pat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>;
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def : Pat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>;
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def : Pat<(i64 (extloadi16_a addr:$src)), (LH64 addr:$src)>;
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@ -218,7 +226,7 @@ let Predicates = [NotN64] in {
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def : Pat<(i64 (extloadi32_u addr:$src)), (ULW64 addr:$src)>;
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def : Pat<(zextloadi32_u addr:$a), (DSRL (DSLL (ULW64 addr:$a), 32), 32)>;
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}
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let Predicates = [IsN64] in {
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let Predicates = [IsN64, HasStandardEncoding] in {
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def : Pat<(i64 (extloadi1 addr:$src)), (LB64_P8 addr:$src)>;
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def : Pat<(i64 (extloadi8 addr:$src)), (LB64_P8 addr:$src)>;
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def : Pat<(i64 (extloadi16_a addr:$src)), (LH64_P8 addr:$src)>;
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@ -270,11 +278,13 @@ defm : SetgePats<CPU64Regs, SLT64, SLTu64>;
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defm : SetgeImmPats<CPU64Regs, SLTi64, SLTiu64>;
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// select MipsDynAlloc
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def : Pat<(MipsDynAlloc addr:$f), (DynAlloc64 addr:$f)>, Requires<[IsN64]>;
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def : Pat<(MipsDynAlloc addr:$f), (DynAlloc64 addr:$f)>,
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Requires<[IsN64, HasStandardEncoding]>;
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// truncate
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def : Pat<(i32 (trunc CPU64Regs:$src)),
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(SLL (EXTRACT_SUBREG CPU64Regs:$src, sub_32), 0)>, Requires<[IsN64]>;
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(SLL (EXTRACT_SUBREG CPU64Regs:$src, sub_32), 0)>,
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Requires<[IsN64, HasStandardEncoding]>;
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// 32-to-64-bit extension
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def : Pat<(i64 (anyext CPURegs:$src)), (SLL64_32 CPURegs:$src)>;
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@ -101,7 +101,7 @@ multiclass MovnPats<RegisterClass CRC, RegisterClass DRC, Instruction MOVNInst,
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// Instantiation of instructions.
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def MOVZ_I_I : CondMovIntInt<CPURegs, CPURegs, 0x0a, "movz">;
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let Predicates = [HasMips64],DecoderNamespace = "Mips64" in {
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let Predicates = [HasMips64, HasStandardEncoding],DecoderNamespace = "Mips64" in {
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def MOVZ_I_I64 : CondMovIntInt<CPURegs, CPU64Regs, 0x0a, "movz">;
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def MOVZ_I64_I : CondMovIntInt<CPU64Regs, CPURegs, 0x0a, "movz"> {
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let isCodeGenOnly = 1;
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@ -112,7 +112,8 @@ let Predicates = [HasMips64],DecoderNamespace = "Mips64" in {
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}
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def MOVN_I_I : CondMovIntInt<CPURegs, CPURegs, 0x0b, "movn">;
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let Predicates = [HasMips64],DecoderNamespace = "Mips64" in {
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let Predicates = [HasMips64, HasStandardEncoding],
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DecoderNamespace = "Mips64" in {
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def MOVN_I_I64 : CondMovIntInt<CPURegs, CPU64Regs, 0x0b, "movn">;
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def MOVN_I64_I : CondMovIntInt<CPU64Regs, CPURegs, 0x0b, "movn"> {
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let isCodeGenOnly = 1;
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@ -124,21 +125,21 @@ let Predicates = [HasMips64],DecoderNamespace = "Mips64" in {
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def MOVZ_I_S : CondMovIntFP<CPURegs, FGR32, 16, 18, "movz.s">;
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def MOVZ_I64_S : CondMovIntFP<CPU64Regs, FGR32, 16, 18, "movz.s">,
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Requires<[HasMips64]> {
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Requires<[HasMips64, HasStandardEncoding]> {
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let DecoderNamespace = "Mips64";
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}
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def MOVN_I_S : CondMovIntFP<CPURegs, FGR32, 16, 19, "movn.s">;
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def MOVN_I64_S : CondMovIntFP<CPU64Regs, FGR32, 16, 19, "movn.s">,
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Requires<[HasMips64]> {
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Requires<[HasMips64, HasStandardEncoding]> {
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let DecoderNamespace = "Mips64";
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}
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let Predicates = [NotFP64bit] in {
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let Predicates = [NotFP64bit, HasStandardEncoding] in {
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def MOVZ_I_D32 : CondMovIntFP<CPURegs, AFGR64, 17, 18, "movz.d">;
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def MOVN_I_D32 : CondMovIntFP<CPURegs, AFGR64, 17, 19, "movn.d">;
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}
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let Predicates = [IsFP64bit],DecoderNamespace = "Mips64" in {
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let Predicates = [IsFP64bit, HasStandardEncoding],DecoderNamespace = "Mips64" in {
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def MOVZ_I_D64 : CondMovIntFP<CPURegs, FGR64, 17, 18, "movz.d">;
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def MOVZ_I64_D64 : CondMovIntFP<CPU64Regs, FGR64, 17, 18, "movz.d"> {
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let isCodeGenOnly = 1;
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@ -151,24 +152,25 @@ let Predicates = [IsFP64bit],DecoderNamespace = "Mips64" in {
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def MOVT_I : CondMovFPInt<CPURegs, MipsCMovFP_T, 1, "movt">;
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def MOVT_I64 : CondMovFPInt<CPU64Regs, MipsCMovFP_T, 1, "movt">,
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Requires<[HasMips64]> {
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Requires<[HasMips64, HasStandardEncoding]> {
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let DecoderNamespace = "Mips64";
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}
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def MOVF_I : CondMovFPInt<CPURegs, MipsCMovFP_F, 0, "movf">;
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def MOVF_I64 : CondMovFPInt<CPU64Regs, MipsCMovFP_F, 0, "movf">,
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Requires<[HasMips64]> {
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Requires<[HasMips64, HasStandardEncoding]> {
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let DecoderNamespace = "Mips64";
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}
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def MOVT_S : CondMovFPFP<FGR32, MipsCMovFP_T, 16, 1, "movt.s">;
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def MOVF_S : CondMovFPFP<FGR32, MipsCMovFP_F, 16, 0, "movf.s">;
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let Predicates = [NotFP64bit] in {
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let Predicates = [NotFP64bit, HasStandardEncoding] in {
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def MOVT_D32 : CondMovFPFP<AFGR64, MipsCMovFP_T, 17, 1, "movt.d">;
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def MOVF_D32 : CondMovFPFP<AFGR64, MipsCMovFP_F, 17, 0, "movf.d">;
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}
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let Predicates = [IsFP64bit], DecoderNamespace = "Mips64" in {
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let Predicates = [IsFP64bit, HasStandardEncoding],
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DecoderNamespace = "Mips64" in {
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def MOVT_D64 : CondMovFPFP<FGR64, MipsCMovFP_T, 17, 1, "movt.d">;
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def MOVF_D64 : CondMovFPFP<FGR64, MipsCMovFP_F, 17, 0, "movf.d">;
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}
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@ -177,7 +179,7 @@ let Predicates = [IsFP64bit], DecoderNamespace = "Mips64" in {
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defm : MovzPats0<CPURegs, CPURegs, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>;
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defm : MovzPats1<CPURegs, CPURegs, MOVZ_I_I, XOR>;
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defm : MovzPats2<CPURegs, CPURegs, MOVZ_I_I, XORi>;
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let Predicates = [HasMips64] in {
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let Predicates = [HasMips64, HasStandardEncoding] in {
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defm : MovzPats0<CPURegs, CPU64Regs, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>;
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defm : MovzPats0<CPU64Regs, CPURegs, MOVZ_I_I, SLT64, SLTu64, SLTi64,
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SLTiu64>;
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@ -192,7 +194,7 @@ let Predicates = [HasMips64] in {
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}
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defm : MovnPats<CPURegs, CPURegs, MOVN_I_I, XOR>;
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let Predicates = [HasMips64] in {
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let Predicates = [HasMips64, HasStandardEncoding] in {
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defm : MovnPats<CPURegs, CPU64Regs, MOVN_I_I64, XOR>;
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defm : MovnPats<CPU64Regs, CPURegs, MOVN_I64_I, XOR64>;
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defm : MovnPats<CPU64Regs, CPU64Regs, MOVN_I64_I64, XOR64>;
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@ -201,19 +203,19 @@ let Predicates = [HasMips64] in {
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defm : MovzPats0<CPURegs, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>;
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defm : MovzPats1<CPURegs, FGR32, MOVZ_I_S, XOR>;
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defm : MovnPats<CPURegs, FGR32, MOVN_I_S, XOR>;
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let Predicates = [HasMips64] in {
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let Predicates = [HasMips64, HasStandardEncoding] in {
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defm : MovzPats0<CPU64Regs, FGR32, MOVZ_I_S, SLT64, SLTu64, SLTi64,
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SLTiu64>;
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defm : MovzPats1<CPU64Regs, FGR32, MOVZ_I64_S, XOR64>;
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defm : MovnPats<CPU64Regs, FGR32, MOVN_I64_S, XOR64>;
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}
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let Predicates = [NotFP64bit] in {
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let Predicates = [NotFP64bit, HasStandardEncoding] in {
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defm : MovzPats0<CPURegs, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu>;
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defm : MovzPats1<CPURegs, AFGR64, MOVZ_I_D32, XOR>;
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defm : MovnPats<CPURegs, AFGR64, MOVN_I_D32, XOR>;
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}
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let Predicates = [IsFP64bit] in {
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let Predicates = [IsFP64bit, HasStandardEncoding] in {
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defm : MovzPats0<CPURegs, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu>;
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defm : MovzPats0<CPU64Regs, FGR64, MOVZ_I_D64, SLT64, SLTu64, SLTi64,
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SLTiu64>;
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@ -117,15 +117,15 @@ class FPIdxStore<bits<6> funct, string opstr, RegisterClass DRC,
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multiclass FFR1_W_M<bits<6> funct, string opstr> {
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def _S : FFR1<funct, 16, opstr, "w.s", FGR32, FGR32>;
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def _D32 : FFR1<funct, 17, opstr, "w.d", FGR32, AFGR64>,
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Requires<[NotFP64bit]>;
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Requires<[NotFP64bit, HasStandardEncoding]>;
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def _D64 : FFR1<funct, 17, opstr, "w.d", FGR32, FGR64>,
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Requires<[IsFP64bit]> {
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Requires<[IsFP64bit, HasStandardEncoding]> {
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let DecoderNamespace = "Mips64";
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}
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}
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// Instructions that convert an FP value to 64-bit fixed point.
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let Predicates = [IsFP64bit], DecoderNamespace = "Mips64" in
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let Predicates = [IsFP64bit, HasStandardEncoding], DecoderNamespace = "Mips64" in
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multiclass FFR1_L_M<bits<6> funct, string opstr> {
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def _S : FFR1<funct, 16, opstr, "l.s", FGR64, FGR32>;
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def _D64 : FFR1<funct, 17, opstr, "l.d", FGR64, FGR64>;
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@ -135,9 +135,9 @@ multiclass FFR1_L_M<bits<6> funct, string opstr> {
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multiclass FFR1P_M<bits<6> funct, string opstr, SDNode OpNode> {
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def _S : FFR1P<funct, 16, opstr, "s", FGR32, FGR32, OpNode>;
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def _D32 : FFR1P<funct, 17, opstr, "d", AFGR64, AFGR64, OpNode>,
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Requires<[NotFP64bit]>;
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Requires<[NotFP64bit, HasStandardEncoding]>;
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def _D64 : FFR1P<funct, 17, opstr, "d", FGR64, FGR64, OpNode>,
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Requires<[IsFP64bit]> {
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Requires<[IsFP64bit, HasStandardEncoding]> {
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let DecoderNamespace = "Mips64";
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}
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}
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@ -146,9 +146,9 @@ multiclass FFR2P_M<bits<6> funct, string opstr, SDNode OpNode, bit isComm = 0> {
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let isCommutable = isComm in {
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def _S : FFR2P<funct, 16, opstr, "s", FGR32, OpNode>;
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def _D32 : FFR2P<funct, 17, opstr, "d", AFGR64, OpNode>,
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Requires<[NotFP64bit]>;
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Requires<[NotFP64bit, HasStandardEncoding]>;
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def _D64 : FFR2P<funct, 17, opstr, "d", FGR64, OpNode>,
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Requires<[IsFP64bit]> {
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Requires<[IsFP64bit, HasStandardEncoding]> {
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let DecoderNamespace = "Mips64";
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}
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}
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@ -185,13 +185,13 @@ def CVT_S_W : FFR1<0x20, 20, "cvt", "s.w", FGR32, FGR32>;
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def CVT_L_S : FFR1<0x25, 16, "cvt", "l.s", FGR64, FGR32>;
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def CVT_L_D64: FFR1<0x25, 17, "cvt", "l.d", FGR64, FGR64>;
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let Predicates = [NotFP64bit] in {
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let Predicates = [NotFP64bit, HasStandardEncoding] in {
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def CVT_S_D32 : FFR1<0x20, 17, "cvt", "s.d", FGR32, AFGR64>;
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def CVT_D32_W : FFR1<0x21, 20, "cvt", "d.w", AFGR64, FGR32>;
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def CVT_D32_S : FFR1<0x21, 16, "cvt", "d.s", AFGR64, FGR32>;
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}
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let Predicates = [IsFP64bit], DecoderNamespace = "Mips64" in {
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let Predicates = [IsFP64bit, HasStandardEncoding], DecoderNamespace = "Mips64" in {
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def CVT_S_D64 : FFR1<0x20, 17, "cvt", "s.d", FGR32, FGR64>;
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def CVT_S_L : FFR1<0x20, 21, "cvt", "s.l", FGR32, FGR64>;
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def CVT_D64_W : FFR1<0x21, 20, "cvt", "d.w", FGR64, FGR32>;
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@ -199,7 +199,7 @@ let Predicates = [IsFP64bit], DecoderNamespace = "Mips64" in {
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def CVT_D64_L : FFR1<0x21, 21, "cvt", "d.l", FGR64, FGR64>;
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}
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let Predicates = [NoNaNsFPMath] in {
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let Predicates = [NoNaNsFPMath, HasStandardEncoding] in {
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defm FABS : FFR1P_M<0x5, "abs", fabs>;
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defm FNEG : FFR1P_M<0x7, "neg", fneg>;
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}
|
||||
@ -242,14 +242,14 @@ def DMTC1 : FFRGPR<0x05, (outs FGR64:$fs), (ins CPU64Regs:$rt),
|
||||
|
||||
def FMOV_S : FFR1<0x6, 16, "mov", "s", FGR32, FGR32>;
|
||||
def FMOV_D32 : FFR1<0x6, 17, "mov", "d", AFGR64, AFGR64>,
|
||||
Requires<[NotFP64bit]>;
|
||||
Requires<[NotFP64bit, HasStandardEncoding]>;
|
||||
def FMOV_D64 : FFR1<0x6, 17, "mov", "d", FGR64, FGR64>,
|
||||
Requires<[IsFP64bit]> {
|
||||
Requires<[IsFP64bit, HasStandardEncoding]> {
|
||||
let DecoderNamespace = "Mips64";
|
||||
}
|
||||
|
||||
/// Floating Point Memory Instructions
|
||||
let Predicates = [IsN64], DecoderNamespace = "Mips64" in {
|
||||
let Predicates = [IsN64, HasStandardEncoding], DecoderNamespace = "Mips64" in {
|
||||
def LWC1_P8 : FPLoad<0x31, "lwc1", FGR32, mem64>;
|
||||
def SWC1_P8 : FPStore<0x39, "swc1", FGR32, mem64>;
|
||||
def LDC164_P8 : FPLoad<0x35, "ldc1", FGR64, mem64> {
|
||||
@ -260,41 +260,42 @@ let Predicates = [IsN64], DecoderNamespace = "Mips64" in {
|
||||
}
|
||||
}
|
||||
|
||||
let Predicates = [NotN64] in {
|
||||
let Predicates = [NotN64, HasStandardEncoding] in {
|
||||
def LWC1 : FPLoad<0x31, "lwc1", FGR32, mem>;
|
||||
def SWC1 : FPStore<0x39, "swc1", FGR32, mem>;
|
||||
}
|
||||
|
||||
let Predicates = [NotN64, HasMips64], DecoderNamespace = "Mips64" in {
|
||||
let Predicates = [NotN64, HasMips64, HasStandardEncoding],
|
||||
DecoderNamespace = "Mips64" in {
|
||||
def LDC164 : FPLoad<0x35, "ldc1", FGR64, mem>;
|
||||
def SDC164 : FPStore<0x3d, "sdc1", FGR64, mem>;
|
||||
}
|
||||
|
||||
let Predicates = [NotN64, NotMips64] in {
|
||||
let Predicates = [NotN64, NotMips64, HasStandardEncoding] in {
|
||||
def LDC1 : FPLoad<0x35, "ldc1", AFGR64, mem>;
|
||||
def SDC1 : FPStore<0x3d, "sdc1", AFGR64, mem>;
|
||||
}
|
||||
|
||||
// Indexed loads and stores.
|
||||
let Predicates = [HasMips32r2Or64] in {
|
||||
let Predicates = [HasMips32r2Or64, HasStandardEncoding] in {
|
||||
def LWXC1 : FPIdxLoad<0x0, "lwxc1", FGR32, CPURegs, load_a>;
|
||||
def LUXC1 : FPIdxLoad<0x5, "luxc1", FGR32, CPURegs, load_u>;
|
||||
def SWXC1 : FPIdxStore<0x8, "swxc1", FGR32, CPURegs, store_a>;
|
||||
def SUXC1 : FPIdxStore<0xd, "suxc1", FGR32, CPURegs, store_u>;
|
||||
}
|
||||
|
||||
let Predicates = [HasMips32r2, NotMips64] in {
|
||||
let Predicates = [HasMips32r2, NotMips64, HasStandardEncoding] in {
|
||||
def LDXC1 : FPIdxLoad<0x1, "ldxc1", AFGR64, CPURegs, load_a>;
|
||||
def SDXC1 : FPIdxStore<0x9, "sdxc1", AFGR64, CPURegs, store_a>;
|
||||
}
|
||||
|
||||
let Predicates = [HasMips64, NotN64], DecoderNamespace="Mips64" in {
|
||||
let Predicates = [HasMips64, NotN64, HasStandardEncoding], DecoderNamespace="Mips64" in {
|
||||
def LDXC164 : FPIdxLoad<0x1, "ldxc1", FGR64, CPURegs, load_a>;
|
||||
def SDXC164 : FPIdxStore<0x9, "sdxc1", FGR64, CPURegs, store_a>;
|
||||
}
|
||||
|
||||
// n64
|
||||
let Predicates = [IsN64], isCodeGenOnly=1 in {
|
||||
let Predicates = [IsN64, HasStandardEncoding], isCodeGenOnly=1 in {
|
||||
def LWXC1_P8 : FPIdxLoad<0x0, "lwxc1", FGR32, CPU64Regs, load_a>;
|
||||
def LUXC1_P8 : FPIdxLoad<0x5, "luxc1", FGR32, CPU64Regs, load_u>;
|
||||
def LDXC164_P8 : FPIdxLoad<0x1, "ldxc1", FGR64, CPU64Regs, load_a>;
|
||||
@ -309,32 +310,33 @@ defm FDIV : FFR2P_M<0x03, "div", fdiv>;
|
||||
defm FMUL : FFR2P_M<0x02, "mul", fmul, 1>;
|
||||
defm FSUB : FFR2P_M<0x01, "sub", fsub>;
|
||||
|
||||
let Predicates = [HasMips32r2] in {
|
||||
let Predicates = [HasMips32r2, HasStandardEncoding] in {
|
||||
def MADD_S : FMADDSUB<0x4, 0, "madd", "s", fadd, FGR32>;
|
||||
def MSUB_S : FMADDSUB<0x5, 0, "msub", "s", fsub, FGR32>;
|
||||
}
|
||||
|
||||
let Predicates = [HasMips32r2, NoNaNsFPMath] in {
|
||||
let Predicates = [HasMips32r2, NoNaNsFPMath, HasStandardEncoding] in {
|
||||
def NMADD_S : FNMADDSUB<0x6, 0, "nmadd", "s", fadd, FGR32>;
|
||||
def NMSUB_S : FNMADDSUB<0x7, 0, "nmsub", "s", fsub, FGR32>;
|
||||
}
|
||||
|
||||
let Predicates = [HasMips32r2, NotFP64bit] in {
|
||||
let Predicates = [HasMips32r2, NotFP64bit, HasStandardEncoding] in {
|
||||
def MADD_D32 : FMADDSUB<0x4, 1, "madd", "d", fadd, AFGR64>;
|
||||
def MSUB_D32 : FMADDSUB<0x5, 1, "msub", "d", fsub, AFGR64>;
|
||||
}
|
||||
|
||||
let Predicates = [HasMips32r2, NotFP64bit, NoNaNsFPMath] in {
|
||||
let Predicates = [HasMips32r2, NotFP64bit, NoNaNsFPMath, HasStandardEncoding] in {
|
||||
def NMADD_D32 : FNMADDSUB<0x6, 1, "nmadd", "d", fadd, AFGR64>;
|
||||
def NMSUB_D32 : FNMADDSUB<0x7, 1, "nmsub", "d", fsub, AFGR64>;
|
||||
}
|
||||
|
||||
let Predicates = [HasMips32r2, IsFP64bit], isCodeGenOnly=1 in {
|
||||
let Predicates = [HasMips32r2, IsFP64bit, HasStandardEncoding], isCodeGenOnly=1 in {
|
||||
def MADD_D64 : FMADDSUB<0x4, 1, "madd", "d", fadd, FGR64>;
|
||||
def MSUB_D64 : FMADDSUB<0x5, 1, "msub", "d", fsub, FGR64>;
|
||||
}
|
||||
|
||||
let Predicates = [HasMips32r2, IsFP64bit, NoNaNsFPMath], isCodeGenOnly=1 in {
|
||||
let Predicates = [HasMips32r2, IsFP64bit, NoNaNsFPMath, HasStandardEncoding],
|
||||
isCodeGenOnly=1 in {
|
||||
def NMADD_D64 : FNMADDSUB<0x6, 1, "nmadd", "d", fadd, FGR64>;
|
||||
def NMSUB_D64 : FNMADDSUB<0x7, 1, "nmsub", "d", fsub, FGR64>;
|
||||
}
|
||||
@ -391,8 +393,10 @@ class FCMP<bits<5> fmt, RegisterClass RC, string typestr> :
|
||||
/// Floating Point Compare
|
||||
let Defs=[FCR31] in {
|
||||
def FCMP_S32 : FCMP<0x10, FGR32, "s">;
|
||||
def FCMP_D32 : FCMP<0x11, AFGR64, "d">, Requires<[NotFP64bit]>;
|
||||
def FCMP_D64 : FCMP<0x11, FGR64, "d">, Requires<[IsFP64bit]> {
|
||||
def FCMP_D32 : FCMP<0x11, AFGR64, "d">,
|
||||
Requires<[NotFP64bit, HasStandardEncoding]>;
|
||||
def FCMP_D64 : FCMP<0x11, FGR64, "d">,
|
||||
Requires<[IsFP64bit, HasStandardEncoding]> {
|
||||
let DecoderNamespace = "Mips64";
|
||||
}
|
||||
}
|
||||
@ -429,14 +433,14 @@ def : Pat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>;
|
||||
def : Pat<(f32 (sint_to_fp CPURegs:$src)), (CVT_S_W (MTC1 CPURegs:$src))>;
|
||||
def : Pat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_S FGR32:$src))>;
|
||||
|
||||
let Predicates = [NotFP64bit] in {
|
||||
let Predicates = [NotFP64bit, HasStandardEncoding] in {
|
||||
def : Pat<(f64 (sint_to_fp CPURegs:$src)), (CVT_D32_W (MTC1 CPURegs:$src))>;
|
||||
def : Pat<(i32 (fp_to_sint AFGR64:$src)), (MFC1 (TRUNC_W_D32 AFGR64:$src))>;
|
||||
def : Pat<(f32 (fround AFGR64:$src)), (CVT_S_D32 AFGR64:$src)>;
|
||||
def : Pat<(f64 (fextend FGR32:$src)), (CVT_D32_S FGR32:$src)>;
|
||||
}
|
||||
|
||||
let Predicates = [IsFP64bit] in {
|
||||
let Predicates = [IsFP64bit, HasStandardEncoding] in {
|
||||
def : Pat<(f64 fpimm0), (DMTC1 ZERO_64)>;
|
||||
def : Pat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>;
|
||||
|
||||
@ -455,13 +459,13 @@ let Predicates = [IsFP64bit] in {
|
||||
}
|
||||
|
||||
// Patterns for unaligned floating point loads and stores.
|
||||
let Predicates = [HasMips32r2Or64, NotN64] in {
|
||||
let Predicates = [HasMips32r2Or64, NotN64, HasStandardEncoding] in {
|
||||
def : Pat<(f32 (load_u CPURegs:$addr)), (LUXC1 CPURegs:$addr, ZERO)>;
|
||||
def : Pat<(store_u FGR32:$src, CPURegs:$addr),
|
||||
(SUXC1 FGR32:$src, CPURegs:$addr, ZERO)>;
|
||||
}
|
||||
|
||||
let Predicates = [IsN64] in {
|
||||
let Predicates = [IsN64, HasStandardEncoding] in {
|
||||
def : Pat<(f32 (load_u CPU64Regs:$addr)), (LUXC1_P8 CPU64Regs:$addr, ZERO_64)>;
|
||||
def : Pat<(store_u FGR32:$src, CPU64Regs:$addr),
|
||||
(SUXC1_P8 FGR32:$src, CPU64Regs:$addr, ZERO_64)>;
|
||||
|
||||
@ -70,6 +70,9 @@ class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
|
||||
let DecoderNamespace = "Mips";
|
||||
|
||||
field bits<32> SoftFail = 0;
|
||||
|
||||
let Predicates = [HasStandardEncoding];
|
||||
|
||||
}
|
||||
|
||||
// Mips Pseudo Instructions Format
|
||||
|
||||
@ -11,11 +11,6 @@
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Instruction format superclass
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
include "MipsInstrFormats.td"
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Mips profiles and nodes
|
||||
@ -151,6 +146,15 @@ def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
|
||||
AssemblerPredicate<"FeatureMips32">;
|
||||
def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
|
||||
AssemblerPredicate<"FeatureMips32">;
|
||||
def HasStandardEncoding:
|
||||
Predicate<"Subtarget.hasStandardEncoding()">,
|
||||
AssemblerPredicate<"FeatureMips32,FeatureMips32r2,FeatureMips64"> ;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Instruction format superclass
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
include "MipsInstrFormats.td"
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Mips Operand, Complex Patterns and Transformations Definitions.
|
||||
@ -430,9 +434,9 @@ class StoreUnAlign<bits<6> op, RegisterClass RC, Operand MemOpnd>:
|
||||
multiclass LoadM32<bits<6> op, string instr_asm, PatFrag OpNode,
|
||||
bit Pseudo = 0> {
|
||||
def #NAME# : LoadM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>,
|
||||
Requires<[NotN64]>;
|
||||
Requires<[NotN64, HasStandardEncoding]>;
|
||||
def _P8 : LoadM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>,
|
||||
Requires<[IsN64]> {
|
||||
Requires<[IsN64, HasStandardEncoding]> {
|
||||
let DecoderNamespace = "Mips64";
|
||||
let isCodeGenOnly = 1;
|
||||
}
|
||||
@ -442,9 +446,9 @@ multiclass LoadM32<bits<6> op, string instr_asm, PatFrag OpNode,
|
||||
multiclass LoadM64<bits<6> op, string instr_asm, PatFrag OpNode,
|
||||
bit Pseudo = 0> {
|
||||
def #NAME# : LoadM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>,
|
||||
Requires<[NotN64]>;
|
||||
Requires<[NotN64, HasStandardEncoding]>;
|
||||
def _P8 : LoadM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>,
|
||||
Requires<[IsN64]> {
|
||||
Requires<[IsN64, HasStandardEncoding]> {
|
||||
let DecoderNamespace = "Mips64";
|
||||
let isCodeGenOnly = 1;
|
||||
}
|
||||
@ -453,9 +457,9 @@ multiclass LoadM64<bits<6> op, string instr_asm, PatFrag OpNode,
|
||||
// 32-bit load.
|
||||
multiclass LoadUnAlign32<bits<6> op> {
|
||||
def #NAME# : LoadUnAlign<op, CPURegs, mem>,
|
||||
Requires<[NotN64]>;
|
||||
Requires<[NotN64, HasStandardEncoding]>;
|
||||
def _P8 : LoadUnAlign<op, CPURegs, mem64>,
|
||||
Requires<[IsN64]> {
|
||||
Requires<[IsN64, HasStandardEncoding]> {
|
||||
let DecoderNamespace = "Mips64";
|
||||
let isCodeGenOnly = 1;
|
||||
}
|
||||
@ -464,9 +468,9 @@ multiclass LoadUnAlign32<bits<6> op> {
|
||||
multiclass StoreM32<bits<6> op, string instr_asm, PatFrag OpNode,
|
||||
bit Pseudo = 0> {
|
||||
def #NAME# : StoreM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>,
|
||||
Requires<[NotN64]>;
|
||||
Requires<[NotN64, HasStandardEncoding]>;
|
||||
def _P8 : StoreM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>,
|
||||
Requires<[IsN64]> {
|
||||
Requires<[IsN64, HasStandardEncoding]> {
|
||||
let DecoderNamespace = "Mips64";
|
||||
let isCodeGenOnly = 1;
|
||||
}
|
||||
@ -476,9 +480,9 @@ multiclass StoreM32<bits<6> op, string instr_asm, PatFrag OpNode,
|
||||
multiclass StoreM64<bits<6> op, string instr_asm, PatFrag OpNode,
|
||||
bit Pseudo = 0> {
|
||||
def #NAME# : StoreM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>,
|
||||
Requires<[NotN64]>;
|
||||
Requires<[NotN64, HasStandardEncoding]>;
|
||||
def _P8 : StoreM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>,
|
||||
Requires<[IsN64]> {
|
||||
Requires<[IsN64, HasStandardEncoding]> {
|
||||
let DecoderNamespace = "Mips64";
|
||||
let isCodeGenOnly = 1;
|
||||
}
|
||||
@ -487,9 +491,9 @@ multiclass StoreM64<bits<6> op, string instr_asm, PatFrag OpNode,
|
||||
// 32-bit store.
|
||||
multiclass StoreUnAlign32<bits<6> op> {
|
||||
def #NAME# : StoreUnAlign<op, CPURegs, mem>,
|
||||
Requires<[NotN64]>;
|
||||
Requires<[NotN64, HasStandardEncoding]>;
|
||||
def _P8 : StoreUnAlign<op, CPURegs, mem64>,
|
||||
Requires<[IsN64]> {
|
||||
Requires<[IsN64, HasStandardEncoding]> {
|
||||
let DecoderNamespace = "Mips64";
|
||||
let isCodeGenOnly = 1;
|
||||
}
|
||||
@ -541,7 +545,7 @@ class JumpFJ<bits<6> op, string instr_asm>:
|
||||
let isTerminator=1;
|
||||
let isBarrier=1;
|
||||
let hasDelaySlot = 1;
|
||||
let Predicates = [RelocStatic];
|
||||
let Predicates = [RelocStatic, HasStandardEncoding];
|
||||
let DecoderMethod = "DecodeJumpTarget";
|
||||
}
|
||||
|
||||
@ -555,7 +559,7 @@ class UncondBranch<bits<6> op, string instr_asm>:
|
||||
let isTerminator = 1;
|
||||
let isBarrier = 1;
|
||||
let hasDelaySlot = 1;
|
||||
let Predicates = [RelocPIC];
|
||||
let Predicates = [RelocPIC, HasStandardEncoding];
|
||||
}
|
||||
|
||||
let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1,
|
||||
@ -653,7 +657,7 @@ class CountLeading0<bits<6> func, string instr_asm, RegisterClass RC>:
|
||||
FR<0x1c, func, (outs RC:$rd), (ins RC:$rs),
|
||||
!strconcat(instr_asm, "\t$rd, $rs"),
|
||||
[(set RC:$rd, (ctlz RC:$rs))], IIAlu>,
|
||||
Requires<[HasBitCount]> {
|
||||
Requires<[HasBitCount, HasStandardEncoding]> {
|
||||
let shamt = 0;
|
||||
let rt = rd;
|
||||
}
|
||||
@ -662,7 +666,7 @@ class CountLeading1<bits<6> func, string instr_asm, RegisterClass RC>:
|
||||
FR<0x1c, func, (outs RC:$rd), (ins RC:$rs),
|
||||
!strconcat(instr_asm, "\t$rd, $rs"),
|
||||
[(set RC:$rd, (ctlz (not RC:$rs)))], IIAlu>,
|
||||
Requires<[HasBitCount]> {
|
||||
Requires<[HasBitCount, HasStandardEncoding]> {
|
||||
let shamt = 0;
|
||||
let rt = rd;
|
||||
}
|
||||
@ -675,7 +679,7 @@ class SignExtInReg<bits<5> sa, string instr_asm, ValueType vt,
|
||||
[(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary> {
|
||||
let rs = 0;
|
||||
let shamt = sa;
|
||||
let Predicates = [HasSEInReg];
|
||||
let Predicates = [HasSEInReg, HasStandardEncoding];
|
||||
}
|
||||
|
||||
// Subword Swap
|
||||
@ -684,7 +688,7 @@ class SubwordSwap<bits<6> func, bits<5> sa, string instr_asm, RegisterClass RC>:
|
||||
!strconcat(instr_asm, "\t$rd, $rt"), [], NoItinerary> {
|
||||
let rs = 0;
|
||||
let shamt = sa;
|
||||
let Predicates = [HasSwap];
|
||||
let Predicates = [HasSwap, HasStandardEncoding];
|
||||
let neverHasSideEffects = 1;
|
||||
}
|
||||
|
||||
@ -705,7 +709,7 @@ class ExtBase<bits<6> _funct, string instr_asm, RegisterClass RC>:
|
||||
bits<5> sz;
|
||||
let rd = sz;
|
||||
let shamt = pos;
|
||||
let Predicates = [HasMips32r2];
|
||||
let Predicates = [HasMips32r2, HasStandardEncoding];
|
||||
}
|
||||
|
||||
class InsBase<bits<6> _funct, string instr_asm, RegisterClass RC>:
|
||||
@ -718,7 +722,7 @@ class InsBase<bits<6> _funct, string instr_asm, RegisterClass RC>:
|
||||
bits<5> sz;
|
||||
let rd = sz;
|
||||
let shamt = pos;
|
||||
let Predicates = [HasMips32r2];
|
||||
let Predicates = [HasMips32r2, HasStandardEncoding];
|
||||
let Constraints = "$src = $rt";
|
||||
}
|
||||
|
||||
@ -730,8 +734,10 @@ class Atomic2Ops<PatFrag Op, string Opstr, RegisterClass DRC,
|
||||
[(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>;
|
||||
|
||||
multiclass Atomic2Ops32<PatFrag Op, string Opstr> {
|
||||
def #NAME# : Atomic2Ops<Op, Opstr, CPURegs, CPURegs>, Requires<[NotN64]>;
|
||||
def _P8 : Atomic2Ops<Op, Opstr, CPURegs, CPU64Regs>, Requires<[IsN64]> {
|
||||
def #NAME# : Atomic2Ops<Op, Opstr, CPURegs, CPURegs>,
|
||||
Requires<[NotN64, HasStandardEncoding]>;
|
||||
def _P8 : Atomic2Ops<Op, Opstr, CPURegs, CPU64Regs>,
|
||||
Requires<[IsN64, HasStandardEncoding]> {
|
||||
let DecoderNamespace = "Mips64";
|
||||
}
|
||||
}
|
||||
@ -744,8 +750,10 @@ class AtomicCmpSwap<PatFrag Op, string Width, RegisterClass DRC,
|
||||
[(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>;
|
||||
|
||||
multiclass AtomicCmpSwap32<PatFrag Op, string Width> {
|
||||
def #NAME# : AtomicCmpSwap<Op, Width, CPURegs, CPURegs>, Requires<[NotN64]>;
|
||||
def _P8 : AtomicCmpSwap<Op, Width, CPURegs, CPU64Regs>, Requires<[IsN64]> {
|
||||
def #NAME# : AtomicCmpSwap<Op, Width, CPURegs, CPURegs>,
|
||||
Requires<[NotN64, HasStandardEncoding]>;
|
||||
def _P8 : AtomicCmpSwap<Op, Width, CPURegs, CPU64Regs>,
|
||||
Requires<[IsN64, HasStandardEncoding]> {
|
||||
let DecoderNamespace = "Mips64";
|
||||
}
|
||||
}
|
||||
@ -876,7 +884,7 @@ def SRLV : shift_rotate_reg<0x06, 0x00, "srlv", srl, CPURegs>;
|
||||
def SRAV : shift_rotate_reg<0x07, 0x00, "srav", sra, CPURegs>;
|
||||
|
||||
// Rotate Instructions
|
||||
let Predicates = [HasMips32r2] in {
|
||||
let Predicates = [HasMips32r2, HasStandardEncoding] in {
|
||||
def ROTR : shift_rotate_imm32<0x02, 0x01, "rotr", rotr>;
|
||||
def ROTRV : shift_rotate_reg<0x06, 0x01, "rotrv", rotr, CPURegs>;
|
||||
}
|
||||
@ -917,13 +925,17 @@ def SYNC : MipsInst<(outs), (ins i32imm:$stype), "sync $stype",
|
||||
}
|
||||
|
||||
/// Load-linked, Store-conditional
|
||||
def LL : LLBase<0x30, "ll", CPURegs, mem>, Requires<[NotN64]>;
|
||||
def LL_P8 : LLBase<0x30, "ll", CPURegs, mem64>, Requires<[IsN64]> {
|
||||
def LL : LLBase<0x30, "ll", CPURegs, mem>,
|
||||
Requires<[NotN64, HasStandardEncoding]>;
|
||||
def LL_P8 : LLBase<0x30, "ll", CPURegs, mem64>,
|
||||
Requires<[IsN64, HasStandardEncoding]> {
|
||||
let DecoderNamespace = "Mips64";
|
||||
}
|
||||
|
||||
def SC : SCBase<0x38, "sc", CPURegs, mem>, Requires<[NotN64]>;
|
||||
def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>, Requires<[IsN64]> {
|
||||
def SC : SCBase<0x38, "sc", CPURegs, mem>,
|
||||
Requires<[NotN64, HasStandardEncoding]>;
|
||||
def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>,
|
||||
Requires<[IsN64, HasStandardEncoding]> {
|
||||
let DecoderNamespace = "Mips64";
|
||||
}
|
||||
|
||||
@ -999,7 +1011,7 @@ def MSUBU : MArithR<5, "msubu", MipsMSubu>;
|
||||
// MUL is a assembly macro in the current used ISAs. In recent ISA's
|
||||
// it is a real instruction.
|
||||
def MUL : ArithLogicR<0x1c, 0x02, "mul", mul, IIImul, CPURegs, 1>,
|
||||
Requires<[HasMips32]>;
|
||||
Requires<[HasMips32, HasStandardEncoding]>;
|
||||
|
||||
def RDHWR : ReadHardware<CPURegs, HWRegs>;
|
||||
|
||||
@ -1085,13 +1097,13 @@ def : Pat<(not CPURegs:$in),
|
||||
(NOR CPURegs:$in, ZERO)>;
|
||||
|
||||
// extended loads
|
||||
let Predicates = [NotN64] in {
|
||||
let Predicates = [NotN64, HasStandardEncoding] in {
|
||||
def : Pat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
|
||||
def : Pat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
|
||||
def : Pat<(i32 (extloadi16_a addr:$src)), (LHu addr:$src)>;
|
||||
def : Pat<(i32 (extloadi16_u addr:$src)), (ULHu addr:$src)>;
|
||||
}
|
||||
let Predicates = [IsN64] in {
|
||||
let Predicates = [IsN64, HasStandardEncoding] in {
|
||||
def : Pat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>;
|
||||
def : Pat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>;
|
||||
def : Pat<(i32 (extloadi16_a addr:$src)), (LHu_P8 addr:$src)>;
|
||||
@ -1099,11 +1111,11 @@ let Predicates = [IsN64] in {
|
||||
}
|
||||
|
||||
// peepholes
|
||||
let Predicates = [NotN64] in {
|
||||
let Predicates = [NotN64, HasStandardEncoding] in {
|
||||
def : Pat<(store_a (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
|
||||
def : Pat<(store_u (i32 0), addr:$dst), (USW ZERO, addr:$dst)>;
|
||||
}
|
||||
let Predicates = [IsN64] in {
|
||||
let Predicates = [IsN64, HasStandardEncoding] in {
|
||||
def : Pat<(store_a (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>;
|
||||
def : Pat<(store_u (i32 0), addr:$dst), (USW_P8 ZERO, addr:$dst)>;
|
||||
}
|
||||
|
||||
@ -130,6 +130,8 @@ public:
|
||||
bool inMips16Mode() const { return InMips16Mode; }
|
||||
bool isLinux() const { return IsLinux; }
|
||||
|
||||
bool hasStandardEncoding() const { return !inMips16Mode(); }
|
||||
|
||||
/// Features related to the presence of specific instructions.
|
||||
bool hasSEInReg() const { return HasSEInReg; }
|
||||
bool hasCondMov() const { return HasCondMov; }
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user