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Avoid generating ISD::SELECT for vector operands to SIGN_EXTEND

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176881 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Relph 2013-03-12 18:17:18 +00:00
parent 2ee69f1be6
commit 1a5c0510ec
1 changed files with 2 additions and 2 deletions
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4
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -4496,8 +4496,8 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
NegOne, DAG.getConstant(0, VT),
cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
if (SCC.getNode()) return SCC;
if (!LegalOperations ||
TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT)))
if (!VT.isVector() && (!LegalOperations ||
TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT))))
return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
DAG.getSetCC(N->getDebugLoc(),
TLI.getSetCCResultType(VT),