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IPRA: Don't assume called function is first call operand
Fixes not finding the called global for AMDGPU call pseudoinstructions, which prevented IPRA from doing much. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311637 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -88,6 +88,19 @@ void RegUsageInfoPropagationPass::getAnalysisUsage(AnalysisUsage &AU) const {
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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// Assumes call instructions have a single reference to a function.
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static const Function *findCalledFunction(const Module &M, MachineInstr &MI) {
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for (MachineOperand &MO : MI.operands()) {
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if (MO.isGlobal())
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return dyn_cast<Function>(MO.getGlobal());
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if (MO.isSymbol())
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return M.getFunction(MO.getSymbolName());
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}
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return nullptr;
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}
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bool RegUsageInfoPropagationPass::runOnMachineFunction(MachineFunction &MF) {
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const Module *M = MF.getFunction()->getParent();
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PhysicalRegisterUsageInfo *PRUI = &getAnalysis<PhysicalRegisterUsageInfo>();
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@ -118,15 +131,14 @@ bool RegUsageInfoPropagationPass::runOnMachineFunction(MachineFunction &MF) {
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Changed = true;
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};
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MachineOperand &Operand = MI.getOperand(0);
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if (Operand.isGlobal())
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UpdateRegMask(cast<Function>(Operand.getGlobal()));
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else if (Operand.isSymbol())
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UpdateRegMask(M->getFunction(Operand.getSymbolName()));
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if (const Function *F = findCalledFunction(*M, MI)) {
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UpdateRegMask(F);
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} else {
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DEBUG(dbgs() << "Failed to find call target function\n");
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}
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DEBUG(dbgs()
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<< "Call Instruction After Register Usage Info Propagation : \n");
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DEBUG(dbgs() << MI << "\n");
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DEBUG(dbgs() << "Call Instruction After Register Usage Info Propagation : "
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<< MI << '\n');
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}
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}
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@ -1,4 +1,4 @@
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -enable-ipra < %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -enable-ipra -amdgpu-sroa=0 < %s | FileCheck -check-prefix=GCN %s
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; Kernels are not called, so there is no call preserved mask.
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; GCN-LABEL: {{^}}kernel:
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@ -9,4 +9,86 @@ entry:
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ret void
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}
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; GCN-LABEL: {{^}}func:
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; GCN: ; NumVgprs: 8
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define void @func() #1 {
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call void asm sideeffect "", "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7}"() #0
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ret void
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}
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; GCN-LABEL: {{^}}kernel_call:
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; GCN-NOT: buffer_store
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; GCN-NOT: buffer_load
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; GCN-NOT: readlane
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; GCN-NOT: writelane
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; GCN: flat_load_dword v8
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; GCN: s_swappc_b64
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; GCN-NOT: buffer_store
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; GCN-NOT: buffer_load
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; GCN-NOT: readlane
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; GCN-NOT: writelane
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; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v8
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; GCN: ; NumSgprs: 37
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; GCN: ; NumVgprs: 9
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define amdgpu_kernel void @kernel_call() #0 {
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%vgpr = load volatile i32, i32 addrspace(1)* undef
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tail call void @func()
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store volatile i32 %vgpr, i32 addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}func_regular_call:
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; GCN-NOT: buffer_store
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; GCN-NOT: buffer_load
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; GCN-NOT: readlane
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; GCN-NOT: writelane
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; GCN: flat_load_dword v8
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; GCN: s_swappc_b64
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; GCN-NOT: buffer_store
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; GCN-NOT: buffer_load
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; GCN-NOT: readlane
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; GCN-NOT: writelane
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; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v8
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; GCN: ; NumSgprs: 32
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; GCN: ; NumVgprs: 9
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define void @func_regular_call() #1 {
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%vgpr = load volatile i32, i32 addrspace(1)* undef
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tail call void @func()
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store volatile i32 %vgpr, i32 addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}func_tail_call:
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; GCN: s_waitcnt
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; GCN-NEXT: s_getpc_b64 s[6:7]
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; GCN-NEXT: s_add_u32 s6,
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; GCN-NEXT: s_addc_u32 s7,
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; GCN-NEXT: s_setpc_b64 s[6:7]
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; GCN: ; NumSgprs: 32
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; GCN: ; NumVgprs: 8
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define void @func_tail_call() #1 {
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tail call void @func()
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ret void
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}
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; GCN-LABEL: {{^}}func_call_tail_call:
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; GCN: flat_load_dword v8
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; GCN: s_swappc_b64
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; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v8
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; GCN: s_setpc_b64
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; GCN: ; NumSgprs: 32
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; GCN: ; NumVgprs: 9
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define void @func_call_tail_call() #1 {
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%vgpr = load volatile i32, i32 addrspace(1)* undef
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tail call void @func()
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store volatile i32 %vgpr, i32 addrspace(1)* undef
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tail call void @func()
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ret void
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind noinline }
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