RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2024-12-26 14:15:53 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Fix Intel asm syntax for the bsr and bsf instructions.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45030 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2007-12-14 15:10:00 +00:00
parent 152804e9c1
commit 1a8001e665
2 changed files with 12 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
lib/Target/X86/X86InstrInfo.td
View File

@ -450,32 +450,32 @@ def XCHG32rm : I<0x87, MRMSrcMem,
// Bit scan instructions.
let Defs = [EFLAGS] in {
def BSF16rr : I<0xBC, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
"bsf{w}\t{$src, $dst||$dst, $src}",
"bsf{w}\t{$src, $dst|$dst, $src}",
[(set GR16:$dst, (X86bsf GR16:$src)), (implicit EFLAGS)]>, TB;
def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
"bsf{w}\t{$src, $dst||$dst, $src}",
"bsf{w}\t{$src, $dst|$dst, $src}",
[(set GR16:$dst, (X86bsf (loadi16 addr:$src))),
(implicit EFLAGS)]>, TB;
def BSF32rr : I<0xBC, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
"bsf{l}\t{$src, $dst||$dst, $src}",
"bsf{l}\t{$src, $dst|$dst, $src}",
[(set GR32:$dst, (X86bsf GR32:$src)), (implicit EFLAGS)]>, TB;
def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
"bsf{l}\t{$src, $dst||$dst, $src}",
"bsf{l}\t{$src, $dst|$dst, $src}",
[(set GR32:$dst, (X86bsf (loadi32 addr:$src))),
(implicit EFLAGS)]>, TB;
def BSR16rr : I<0xBD, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
"bsr{w}\t{$src, $dst||$dst, $src}",
"bsr{w}\t{$src, $dst|$dst, $src}",
[(set GR16:$dst, (X86bsr GR16:$src)), (implicit EFLAGS)]>, TB;
def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
"bsr{w}\t{$src, $dst||$dst, $src}",
"bsr{w}\t{$src, $dst|$dst, $src}",
[(set GR16:$dst, (X86bsr (loadi16 addr:$src))),
(implicit EFLAGS)]>, TB;
def BSR32rr : I<0xBD, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
"bsr{l}\t{$src, $dst||$dst, $src}",
"bsr{l}\t{$src, $dst|$dst, $src}",
[(set GR32:$dst, (X86bsr GR32:$src)), (implicit EFLAGS)]>, TB;
def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
"bsr{l}\t{$src, $dst||$dst, $src}",
"bsr{l}\t{$src, $dst|$dst, $src}",
[(set GR32:$dst, (X86bsr (loadi32 addr:$src))),
(implicit EFLAGS)]>, TB;
} // Defs = [EFLAGS]

8
lib/Target/X86/X86InstrX86-64.td
View File

@ -170,17 +170,17 @@ def XCHG64rm : RI<0x87, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
// Bit scan instructions.
let Defs = [EFLAGS] in {
def BSF64rr : RI<0xBC, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
"bsf{q}\t{$src, $dst||$dst, $src}",
"bsf{q}\t{$src, $dst|$dst, $src}",
[(set GR64:$dst, (X86bsf GR64:$src))]>, TB;
def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
"bsf{q}\t{$src, $dst||$dst, $src}",
"bsf{q}\t{$src, $dst|$dst, $src}",
[(set GR64:$dst, (X86bsf (loadi64 addr:$src)))]>, TB;
def BSR64rr : RI<0xBD, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
"bsr{q}\t{$src, $dst||$dst, $src}",
"bsr{q}\t{$src, $dst|$dst, $src}",
[(set GR64:$dst, (X86bsr GR64:$src))]>, TB;
def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
"bsr{q}\t{$src, $dst||$dst, $src}",
"bsr{q}\t{$src, $dst|$dst, $src}",
[(set GR64:$dst, (X86bsr (loadi64 addr:$src)))]>, TB;
} // Defs = [EFLAGS]