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[AArch64] Combining Load and IntToFp should check for neon availability

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223382 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Weiming Zhao 2014-12-04 20:25:50 +00:00
parent 61f3193001
commit 1b77bb5628
2 changed files with 20 additions and 3 deletions
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7
lib/Target/AArch64/AArch64ISelLowering.cpp
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@ -6951,7 +6951,8 @@ static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
return SDValue(); return SDValue();
} }
static SDValue performIntToFpCombine(SDNode *N, SelectionDAG &DAG) { static SDValue performIntToFpCombine(SDNode *N, SelectionDAG &DAG,
const AArch64Subtarget *Subtarget) {
// First try to optimize away the conversion when it's conditionally from // First try to optimize away the conversion when it's conditionally from
// a constant. Vectors only. // a constant. Vectors only.
SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG); SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
@ -6970,7 +6971,7 @@ static SDValue performIntToFpCombine(SDNode *N, SelectionDAG &DAG) {
// conversion, use a fp load instead and a AdvSIMD scalar {S|U}CVTF instead. // conversion, use a fp load instead and a AdvSIMD scalar {S|U}CVTF instead.
// This eliminates an "integer-to-vector-move UOP and improve throughput. // This eliminates an "integer-to-vector-move UOP and improve throughput.
SDValue N0 = N->getOperand(0); SDValue N0 = N->getOperand(0);
if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && if (Subtarget->hasNEON() && ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
// Do not change the width of a volatile load. // Do not change the width of a volatile load.
!cast<LoadSDNode>(N0)->isVolatile()) { !cast<LoadSDNode>(N0)->isVolatile()) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0); LoadSDNode *LN0 = cast<LoadSDNode>(N0);
@ -8527,7 +8528,7 @@ SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
return performMulCombine(N, DAG, DCI, Subtarget); return performMulCombine(N, DAG, DCI, Subtarget);
case ISD::SINT_TO_FP: case ISD::SINT_TO_FP:
case ISD::UINT_TO_FP: case ISD::UINT_TO_FP:
return performIntToFpCombine(N, DAG); return performIntToFpCombine(N, DAG, Subtarget);
case ISD::OR: case ISD::OR:
return performORCombine(N, DCI, Subtarget); return performORCombine(N, DCI, Subtarget);
case ISD::INTRINSIC_WO_CHAIN: case ISD::INTRINSIC_WO_CHAIN:

16
test/CodeGen/AArch64/aarch64-2014-12-02-combine-soften.ll Normal file
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@ -0,0 +1,16 @@
;RUN: llc <%s -mattr=-neon -mattr=-fp-armv8 | FileCheck %s
target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
target triple = "aarch64"
@t = common global i32 0, align 4
@x = common global i32 0, align 4
define void @foo() {
entry:
;CHECK-LABEL: foo:
;CHECK: __floatsisf
%0 = load i32* @x, align 4
%conv = sitofp i32 %0 to float
store float %conv, float* bitcast (i32* @t to float*), align 4
ret void
}