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[AMDGPU] gfx1010 GCNNSAReassign pass
Convert NSA into non-NSA images. Differential Revision: https://reviews.llvm.org/D61341 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359700 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Stanislav Mekhanoshin
parent
542de76c15
commit
1c29f9f7f5
@ -221,6 +221,9 @@ ModulePass *createAMDGPUOpenCLEnqueuedBlockLoweringPass();
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void initializeAMDGPUOpenCLEnqueuedBlockLoweringPass(PassRegistry &);
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extern char &AMDGPUOpenCLEnqueuedBlockLoweringID;
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void initializeGCNNSAReassignPass(PassRegistry &);
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extern char &GCNNSAReassignID;
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Target &getTheAMDGPUTarget();
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Target &getTheGCNTarget();
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@ -149,6 +149,12 @@ static cl::opt<bool> EnableLowerKernelArguments(
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cl::init(true),
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cl::Hidden);
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static cl::opt<bool> EnableRegReassign(
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"amdgpu-reassign-regs",
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cl::desc("Enable register reassign optimizations on gfx10+"),
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cl::init(true),
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cl::Hidden);
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// Enable atomic optimization
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static cl::opt<bool> EnableAtomicOptimizations(
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"amdgpu-atomic-optimizations",
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@ -228,6 +234,7 @@ extern "C" void LLVMInitializeAMDGPUTarget() {
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initializeAMDGPUUseNativeCallsPass(*PR);
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initializeAMDGPUSimplifyLibCallsPass(*PR);
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initializeAMDGPUInlinerPass(*PR);
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initializeGCNNSAReassignPass(*PR);
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}
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static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
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@ -605,6 +612,7 @@ public:
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void addFastRegAlloc() override;
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void addOptimizedRegAlloc() override;
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void addPreRegAlloc() override;
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bool addPreRewrite() override;
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void addPostRegAlloc() override;
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void addPreSched2() override;
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void addPreEmitPass() override;
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@ -926,6 +934,13 @@ void GCNPassConfig::addOptimizedRegAlloc() {
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TargetPassConfig::addOptimizedRegAlloc();
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}
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bool GCNPassConfig::addPreRewrite() {
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if (EnableRegReassign) {
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addPass(&GCNNSAReassignID);
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}
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return true;
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}
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void GCNPassConfig::addPostRegAlloc() {
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addPass(&SIFixVGPRCopiesID);
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if (getOptLevel() > CodeGenOpt::None)
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@ -116,6 +116,7 @@ add_llvm_target(AMDGPUCodeGen
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SIShrinkInstructions.cpp
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SIWholeQuadMode.cpp
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GCNILPSched.cpp
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GCNNSAReassign.cpp
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GCNDPPCombine.cpp
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SIModeRegister.cpp
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)
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343
lib/Target/AMDGPU/GCNNSAReassign.cpp
Normal file
343
lib/Target/AMDGPU/GCNNSAReassign.cpp
Normal file
@ -0,0 +1,343 @@
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//===-- GCNNSAReassign.cpp - Reassign registers in NSA unstructions -------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Try to reassign registers on GFX10+ from non-sequential to sequential
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/// in NSA image instructions. Later SIShrinkInstructions pass will relace NSA
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/// with sequential versions where possible.
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///
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "AMDGPUSubtarget.h"
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#include "SIInstrInfo.h"
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#include "SIMachineFunctionInfo.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/LiveInterval.h"
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#include "llvm/CodeGen/LiveIntervals.h"
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#include "llvm/CodeGen/LiveRegMatrix.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/VirtRegMap.h"
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#include "llvm/Support/MathExtras.h"
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#include <algorithm>
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using namespace llvm;
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#define DEBUG_TYPE "amdgpu-nsa-reassign"
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STATISTIC(NumNSAInstructions,
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"Number of NSA instructions with non-sequential address found");
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STATISTIC(NumNSAConverted,
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"Number of NSA instructions changed to sequential");
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namespace {
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class GCNNSAReassign : public MachineFunctionPass {
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public:
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static char ID;
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GCNNSAReassign() : MachineFunctionPass(ID) {
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initializeGCNNSAReassignPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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StringRef getPassName() const override { return "GCN NSA Reassign"; }
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.addRequired<LiveIntervals>();
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AU.addRequired<VirtRegMap>();
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AU.addRequired<LiveRegMatrix>();
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AU.setPreservesAll();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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private:
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typedef enum {
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NOT_NSA, // Not an NSA instruction
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FIXED, // NSA which we cannot modify
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NON_CONTIGUOUS, // NSA with non-sequential address which we can try
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// to optimize.
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CONTIGUOUS // NSA with all sequential address registers
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} NSA_Status;
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const GCNSubtarget *ST;
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const MachineRegisterInfo *MRI;
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const SIRegisterInfo *TRI;
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VirtRegMap *VRM;
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LiveRegMatrix *LRM;
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LiveIntervals *LIS;
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unsigned MaxNumVGPRs;
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const MCPhysReg *CSRegs;
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NSA_Status CheckNSA(const MachineInstr &MI, bool Fast = false) const;
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bool tryAssignRegisters(SmallVectorImpl<LiveInterval *> &Intervals,
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unsigned StartReg) const;
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bool canAssign(unsigned StartReg, unsigned NumRegs) const;
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bool scavengeRegs(SmallVectorImpl<LiveInterval *> &Intervals) const;
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};
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} // End anonymous namespace.
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INITIALIZE_PASS_BEGIN(GCNNSAReassign, DEBUG_TYPE, "GCN NSA Reassign",
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false, false)
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INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
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INITIALIZE_PASS_DEPENDENCY(VirtRegMap)
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INITIALIZE_PASS_DEPENDENCY(LiveRegMatrix)
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INITIALIZE_PASS_END(GCNNSAReassign, DEBUG_TYPE, "GCN NSA Reassign",
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false, false)
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char GCNNSAReassign::ID = 0;
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char &llvm::GCNNSAReassignID = GCNNSAReassign::ID;
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bool
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GCNNSAReassign::tryAssignRegisters(SmallVectorImpl<LiveInterval *> &Intervals,
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unsigned StartReg) const {
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unsigned NumRegs = Intervals.size();
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for (unsigned N = 0; N < NumRegs; ++N)
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if (VRM->hasPhys(Intervals[N]->reg))
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LRM->unassign(*Intervals[N]);
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for (unsigned N = 0; N < NumRegs; ++N)
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if (LRM->checkInterference(*Intervals[N], StartReg + N))
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return false;
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for (unsigned N = 0; N < NumRegs; ++N)
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LRM->assign(*Intervals[N], StartReg + N);
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return true;
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}
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bool GCNNSAReassign::canAssign(unsigned StartReg, unsigned NumRegs) const {
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for (unsigned N = 0; N < NumRegs; ++N) {
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unsigned Reg = StartReg + N;
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if (!MRI->isAllocatable(Reg))
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return false;
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for (unsigned I = 0; CSRegs[I]; ++I)
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if (TRI->isSubRegisterEq(Reg, CSRegs[I]) &&
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!LRM->isPhysRegUsed(CSRegs[I]))
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return false;
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}
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return true;
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}
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bool
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GCNNSAReassign::scavengeRegs(SmallVectorImpl<LiveInterval *> &Intervals) const {
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unsigned NumRegs = Intervals.size();
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if (NumRegs > MaxNumVGPRs)
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return false;
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unsigned MaxReg = MaxNumVGPRs - NumRegs + AMDGPU::VGPR0;
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for (unsigned Reg = AMDGPU::VGPR0; Reg <= MaxReg; ++Reg) {
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if (!canAssign(Reg, NumRegs))
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continue;
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if (tryAssignRegisters(Intervals, Reg))
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return true;
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}
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return false;
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}
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GCNNSAReassign::NSA_Status
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GCNNSAReassign::CheckNSA(const MachineInstr &MI, bool Fast) const {
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const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode());
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if (!Info || Info->MIMGEncoding != AMDGPU::MIMGEncGfx10NSA)
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return NSA_Status::NOT_NSA;
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int VAddr0Idx =
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AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);
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unsigned VgprBase = 0;
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bool NSA = false;
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for (unsigned I = 0; I < Info->VAddrDwords; ++I) {
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const MachineOperand &Op = MI.getOperand(VAddr0Idx + I);
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unsigned Reg = Op.getReg();
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if (TargetRegisterInfo::isPhysicalRegister(Reg) || !VRM->isAssignedReg(Reg))
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return NSA_Status::FIXED;
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unsigned PhysReg = VRM->getPhys(Reg);
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if (!Fast) {
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if (!PhysReg)
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return NSA_Status::FIXED;
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// Bail if address is not a VGPR32. That should be possible to extend the
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// optimization to work with subregs of a wider register tuples, but the
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// logic to find free registers will be much more complicated with much
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// less chances for success. That seems reasonable to assume that in most
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// cases a tuple is used because a vector variable contains different
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// parts of an address and it is either already consequitive or cannot
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// be reassigned if not. If needed it is better to rely on register
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// coalescer to process such address tuples.
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if (MRI->getRegClass(Reg) != &AMDGPU::VGPR_32RegClass || Op.getSubReg())
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return NSA_Status::FIXED;
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const MachineInstr *Def = MRI->getUniqueVRegDef(Reg);
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if (Def && Def->isCopy() && Def->getOperand(1).getReg() == PhysReg)
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return NSA_Status::FIXED;
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for (auto U : MRI->use_nodbg_operands(Reg)) {
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if (U.isImplicit())
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return NSA_Status::FIXED;
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const MachineInstr *UseInst = U.getParent();
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if (UseInst->isCopy() && UseInst->getOperand(0).getReg() == PhysReg)
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return NSA_Status::FIXED;
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}
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if (!LIS->hasInterval(Reg))
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return NSA_Status::FIXED;
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}
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if (I == 0)
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VgprBase = PhysReg;
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else if (VgprBase + I != PhysReg)
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NSA = true;
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}
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return NSA ? NSA_Status::NON_CONTIGUOUS : NSA_Status::CONTIGUOUS;
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}
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bool GCNNSAReassign::runOnMachineFunction(MachineFunction &MF) {
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ST = &MF.getSubtarget<GCNSubtarget>();
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if (ST->getGeneration() < GCNSubtarget::GFX10)
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return false;
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MRI = &MF.getRegInfo();
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TRI = ST->getRegisterInfo();
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VRM = &getAnalysis<VirtRegMap>();
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LRM = &getAnalysis<LiveRegMatrix>();
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LIS = &getAnalysis<LiveIntervals>();
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const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
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MaxNumVGPRs = ST->getMaxNumVGPRs(MF);
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MaxNumVGPRs = std::min(ST->getMaxNumVGPRs(MFI->getOccupancy()), MaxNumVGPRs);
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CSRegs = TRI->getCalleeSavedRegs(&MF);
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using Candidate = std::pair<const MachineInstr*, bool>;
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SmallVector<Candidate, 32> Candidates;
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for (const MachineBasicBlock &MBB : MF) {
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for (const MachineInstr &MI : MBB) {
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switch (CheckNSA(MI)) {
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default:
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continue;
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case NSA_Status::CONTIGUOUS:
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Candidates.push_back(std::make_pair(&MI, true));
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break;
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case NSA_Status::NON_CONTIGUOUS:
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Candidates.push_back(std::make_pair(&MI, false));
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++NumNSAInstructions;
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break;
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}
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}
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}
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bool Changed = false;
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for (auto &C : Candidates) {
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if (C.second)
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continue;
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const MachineInstr *MI = C.first;
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if (CheckNSA(*MI, true) == NSA_Status::CONTIGUOUS) {
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// Already happen to be fixed.
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C.second = true;
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++NumNSAConverted;
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continue;
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}
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const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI->getOpcode());
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int VAddr0Idx =
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AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::vaddr0);
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SmallVector<LiveInterval *, 16> Intervals;
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SmallVector<unsigned, 16> OrigRegs;
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SlotIndex MinInd, MaxInd;
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for (unsigned I = 0; I < Info->VAddrDwords; ++I) {
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const MachineOperand &Op = MI->getOperand(VAddr0Idx + I);
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unsigned Reg = Op.getReg();
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LiveInterval *LI = &LIS->getInterval(Reg);
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if (llvm::find(Intervals, LI) != Intervals.end()) {
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// Same register used, unable to make sequential
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Intervals.clear();
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break;
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}
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Intervals.push_back(LI);
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OrigRegs.push_back(VRM->getPhys(Reg));
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MinInd = I ? std::min(MinInd, LI->beginIndex()) : LI->beginIndex();
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MaxInd = I ? std::max(MaxInd, LI->endIndex()) : LI->endIndex();
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}
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if (Intervals.empty())
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continue;
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LLVM_DEBUG(dbgs() << "Attempting to reassign NSA: " << *MI
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<< "\tOriginal allocation:\t";
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for(auto *LI : Intervals)
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dbgs() << " " << llvm::printReg((VRM->getPhys(LI->reg)), TRI);
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dbgs() << '\n');
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bool Success = scavengeRegs(Intervals);
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if (!Success) {
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LLVM_DEBUG(dbgs() << "\tCannot reallocate.\n");
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if (VRM->hasPhys(Intervals.back()->reg)) // Did not change allocation.
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continue;
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} else {
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// Check we did not make it worse for other instructions.
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auto I = std::lower_bound(Candidates.begin(), &C, MinInd,
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[this](const Candidate &C, SlotIndex I) {
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return LIS->getInstructionIndex(*C.first) < I;
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});
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for (auto E = Candidates.end(); Success && I != E &&
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LIS->getInstructionIndex(*I->first) < MaxInd; ++I) {
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if (I->second && CheckNSA(*I->first, true) < NSA_Status::CONTIGUOUS) {
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Success = false;
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LLVM_DEBUG(dbgs() << "\tNSA conversion conflict with " << *I->first);
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}
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}
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}
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if (!Success) {
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for (unsigned I = 0; I < Info->VAddrDwords; ++I)
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if (VRM->hasPhys(Intervals[I]->reg))
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LRM->unassign(*Intervals[I]);
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for (unsigned I = 0; I < Info->VAddrDwords; ++I)
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LRM->assign(*Intervals[I], OrigRegs[I]);
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continue;
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}
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C.second = true;
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++NumNSAConverted;
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LLVM_DEBUG(dbgs() << "\tNew allocation:\t\t ["
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<< llvm::printReg((VRM->getPhys(Intervals.front()->reg)), TRI)
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<< " : "
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<< llvm::printReg((VRM->getPhys(Intervals.back()->reg)), TRI)
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<< "]\n");
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Changed = true;
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}
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return Changed;
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}
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@ -1,10 +1,12 @@
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; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI,SIVI,PRT %s
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; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,SIVI,PRT %s
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; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX900,PRT %s
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; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX6789,SI %s
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; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX6789,GFX8910,SIVI,PRT %s
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; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX6789,PRT %s
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; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-enable-prt-strict-null -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX900,NOPRT %s
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; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefixes=GCN,GFX10 %s
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; GCN-LABEL: {{^}}load_1d:
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; GCN: image_load v[0:3], v0, s[0:7] dmask:0xf unorm{{$}}
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; GFX6789: image_load v[0:3], v0, s[0:7] dmask:0xf unorm{{$}}
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; GFX10: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm ;
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define amdgpu_ps <4 x float> @load_1d(<8 x i32> inreg %rsrc, i32 %s) {
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main_body:
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%v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
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@ -22,7 +24,8 @@ main_body:
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; NOPRT-NOT: v_mov_b32_e32 v1
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; NOPRT-NOT: v_mov_b32_e32 v2
|
||||
; NOPRT-NOT: v_mov_b32_e32 v3
|
||||
; GCN: image_load v[0:4], v{{[0-9]+}}, s[0:7] dmask:0xf unorm tfe{{$}}
|
||||
; GFX6789: image_load v[0:4], v{{[0-9]+}}, s[0:7] dmask:0xf unorm tfe{{$}}
|
||||
; GFX10: image_load v[0:4], v{{[0-9]+}}, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm tfe ;
|
||||
; SIVI: buffer_store_dword v4, off, s[8:11], 0
|
||||
; GFX900: global_store_dword v[{{[0-9]+:[0-9]+}}], v4
|
||||
define amdgpu_ps <4 x float> @load_1d_tfe(<8 x i32> inreg %rsrc, i32 addrspace(1)* inreg %out, i32 %s) {
|
||||
@ -45,7 +48,8 @@ main_body:
|
||||
; NOPRT-NOT: v_mov_b32_e32 v1
|
||||
; NOPRT-NOT: v_mov_b32_e32 v2
|
||||
; NOPRT-NOT: v_mov_b32_e32 v3
|
||||
; GCN: image_load v[0:4], v{{[0-9]+}}, s[0:7] dmask:0xf unorm lwe{{$}}
|
||||
; GFX6789: image_load v[0:4], v{{[0-9]+}}, s[0:7] dmask:0xf unorm lwe{{$}}
|
||||
; GFX10: image_load v[0:4], v{{[0-9]+}}, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm lwe ;
|
||||
; SIVI: buffer_store_dword v4, off, s[8:11], 0
|
||||
; GFX900: global_store_dword v[{{[0-9]+:[0-9]+}}], v4
|
||||
define amdgpu_ps <4 x float> @load_1d_lwe(<8 x i32> inreg %rsrc, i32 addrspace(1)* inreg %out, i32 %s) {
|
||||
@ -58,7 +62,8 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_2d:
|
||||
; GCN: image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm{{$}}
|
||||
; GFX6789: image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm{{$}}
|
||||
; GFX10: image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm ;
|
||||
define amdgpu_ps <4 x float> @load_2d(<8 x i32> inreg %rsrc, i32 %s, i32 %t) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 15, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
@ -76,7 +81,8 @@ main_body:
|
||||
; NOPRT-NOT: v_mov_b32_e32 v1
|
||||
; NOPRT-NOT: v_mov_b32_e32 v2
|
||||
; NOPRT-NOT: v_mov_b32_e32 v3
|
||||
; GCN: image_load v[0:4], v[{{[0-9]+:[0-9]+}}], s[0:7] dmask:0xf unorm tfe{{$}}
|
||||
; GFX6789: image_load v[0:4], v[{{[0-9]+:[0-9]+}}], s[0:7] dmask:0xf unorm tfe{{$}}
|
||||
; GFX10: image_load v[0:4], v[{{[0-9]+:[0-9]+}}], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm tfe ;
|
||||
; SIVI: buffer_store_dword v4, off, s[8:11], 0
|
||||
; GFX900: global_store_dword v[{{[0-9]+:[0-9]+}}], v4
|
||||
define amdgpu_ps <4 x float> @load_2d_tfe(<8 x i32> inreg %rsrc, i32 addrspace(1)* inreg %out, i32 %s, i32 %t) {
|
||||
@ -89,7 +95,8 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_3d:
|
||||
; GCN: image_load v[0:3], v[0:3], s[0:7] dmask:0xf unorm{{$}}
|
||||
; GFX6789: image_load v[0:3], v[0:3], s[0:7] dmask:0xf unorm{{$}}
|
||||
; GFX10: image_load v[0:3], v[0:2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm ;
|
||||
define amdgpu_ps <4 x float> @load_3d(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %r) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i32(i32 15, i32 %s, i32 %t, i32 %r, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
@ -107,7 +114,8 @@ main_body:
|
||||
; NOPRT-NOT: v_mov_b32_e32 v1
|
||||
; NOPRT-NOT: v_mov_b32_e32 v2
|
||||
; NOPRT-NOT: v_mov_b32_e32 v3
|
||||
; GCN: image_load v[0:4], v[{{[0-9]+:[0-9]+}}], s[0:7] dmask:0xf unorm tfe lwe{{$}}
|
||||
; GFX6789: image_load v[0:4], v[{{[0-9]+:[0-9]+}}], s[0:7] dmask:0xf unorm tfe lwe{{$}}
|
||||
; GFX10: image_load v[0:4], v[{{[0-9]+:[0-9]+}}], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm tfe lwe ;
|
||||
; SIVI: buffer_store_dword v4, off, s[8:11], 0
|
||||
; GFX900: global_store_dword v[{{[0-9]+:[0-9]+}}], v4
|
||||
define amdgpu_ps <4 x float> @load_3d_tfe_lwe(<8 x i32> inreg %rsrc, i32 addrspace(1)* inreg %out, i32 %s, i32 %t, i32 %r) {
|
||||
@ -120,7 +128,8 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_cube:
|
||||
; GCN: image_load v[0:3], v[0:3], s[0:7] dmask:0xf unorm da{{$}}
|
||||
; GFX6789: image_load v[0:3], v[0:3], s[0:7] dmask:0xf unorm da{{$}}
|
||||
; GFX10: image_load v[0:3], v[0:2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE unorm ;
|
||||
define amdgpu_ps <4 x float> @load_cube(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %slice) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.load.cube.v4f32.i32(i32 15, i32 %s, i32 %t, i32 %slice, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
@ -138,7 +147,8 @@ main_body:
|
||||
; NOPRT-NOT: v_mov_b32_e32 v1
|
||||
; NOPRT-NOT: v_mov_b32_e32 v2
|
||||
; NOPRT-NOT: v_mov_b32_e32 v3
|
||||
; GCN: image_load v[0:4], v[{{[0-9]+:[0-9]+}}], s[0:7] dmask:0xf unorm lwe da{{$}}
|
||||
; GFX6789: image_load v[0:4], v[{{[0-9]+:[0-9]+}}], s[0:7] dmask:0xf unorm lwe da{{$}}
|
||||
; GFX10: image_load v[0:4], v[{{[0-9]+:[0-9]+}}], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE unorm lwe ;
|
||||
; SIVI: buffer_store_dword v4, off, s[8:11], 0
|
||||
; GFX900: global_store_dword v[{{[0-9]+:[0-9]+}}], v4
|
||||
define amdgpu_ps <4 x float> @load_cube_lwe(<8 x i32> inreg %rsrc, i32 addrspace(1)* inreg %out, i32 %s, i32 %t, i32 %slice) {
|
||||
@ -151,7 +161,8 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_1darray:
|
||||
; GCN: image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm da{{$}}
|
||||
; GFX6789: image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm da{{$}}
|
||||
; GFX10: image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY unorm ;
|
||||
define amdgpu_ps <4 x float> @load_1darray(<8 x i32> inreg %rsrc, i32 %s, i32 %slice) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.load.1darray.v4f32.i32(i32 15, i32 %s, i32 %slice, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
@ -169,7 +180,8 @@ main_body:
|
||||
; NOPRT-NOT: v_mov_b32_e32 v1
|
||||
; NOPRT-NOT: v_mov_b32_e32 v2
|
||||
; NOPRT-NOT: v_mov_b32_e32 v3
|
||||
; GCN: image_load v[0:4], v[{{[0-9]+:[0-9]+}}], s[0:7] dmask:0xf unorm tfe da{{$}}
|
||||
; GFX6789: image_load v[0:4], v[{{[0-9]+:[0-9]+}}], s[0:7] dmask:0xf unorm tfe da{{$}}
|
||||
; GFX10: image_load v[0:4], v[{{[0-9]+:[0-9]+}}], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY unorm tfe ;
|
||||
; SIVI: buffer_store_dword v4, off, s[8:11], 0
|
||||
; GFX900: global_store_dword v[{{[0-9]+:[0-9]+}}], v4
|
||||
define amdgpu_ps <4 x float> @load_1darray_tfe(<8 x i32> inreg %rsrc, i32 addrspace(1)* inreg %out, i32 %s, i32 %slice) {
|
||||
@ -182,7 +194,8 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_2darray:
|
||||
; GCN: image_load v[0:3], v[0:3], s[0:7] dmask:0xf unorm da{{$}}
|
||||
; GFX6789: image_load v[0:3], v[0:3], s[0:7] dmask:0xf unorm da{{$}}
|
||||
; GFX10: image_load v[0:3], v[0:2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY unorm ;
|
||||
define amdgpu_ps <4 x float> @load_2darray(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %slice) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.load.2darray.v4f32.i32(i32 15, i32 %s, i32 %t, i32 %slice, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
@ -200,7 +213,8 @@ main_body:
|
||||
; NOPRT-NOT: v_mov_b32_e32 v1
|
||||
; NOPRT-NOT: v_mov_b32_e32 v2
|
||||
; NOPRT-NOT: v_mov_b32_e32 v3
|
||||
; GCN: image_load v[0:4], v[{{[0-9]+:[0-9]+}}], s[0:7] dmask:0xf unorm lwe da{{$}}
|
||||
; GFX6789: image_load v[0:4], v[{{[0-9]+:[0-9]+}}], s[0:7] dmask:0xf unorm lwe da{{$}}
|
||||
; GFX10: image_load v[0:4], v[{{[0-9]+:[0-9]+}}], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY unorm lwe ;
|
||||
; SIVI: buffer_store_dword v4, off, s[8:11], 0
|
||||
; GFX900: global_store_dword v[{{[0-9]+:[0-9]+}}], v4
|
||||
define amdgpu_ps <4 x float> @load_2darray_lwe(<8 x i32> inreg %rsrc, i32 addrspace(1)* inreg %out, i32 %s, i32 %t, i32 %slice) {
|
||||
@ -213,7 +227,8 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_2dmsaa:
|
||||
; GCN: image_load v[0:3], v[0:3], s[0:7] dmask:0xf unorm{{$}}
|
||||
; GFX6789: image_load v[0:3], v[0:3], s[0:7] dmask:0xf unorm{{$}}
|
||||
; GFX10: image_load v[0:3], v[0:2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA unorm ;
|
||||
define amdgpu_ps <4 x float> @load_2dmsaa(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %fragid) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.load.2dmsaa.v4f32.i32(i32 15, i32 %s, i32 %t, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
@ -231,7 +246,8 @@ main_body:
|
||||
; NOPRT-NOT: v_mov_b32_e32 v1
|
||||
; NOPRT-NOT: v_mov_b32_e32 v2
|
||||
; NOPRT-NOT: v_mov_b32_e32 v3
|
||||
; GCN: image_load v[0:4], v[{{[0-9]+:[0-9]+}}], s[0:7] dmask:0xf unorm tfe lwe{{$}}
|
||||
; GFX6789: image_load v[0:4], v[{{[0-9]+:[0-9]+}}], s[0:7] dmask:0xf unorm tfe lwe{{$}}
|
||||
; GFX10: image_load v[0:4], v[{{[0-9]+:[0-9]+}}], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA unorm tfe lwe ;
|
||||
; SIVI: buffer_store_dword v4, off, s[8:11], 0
|
||||
; GFX900: global_store_dword v[{{[0-9]+:[0-9]+}}], v4
|
||||
define amdgpu_ps <4 x float> @load_2dmsaa_both(<8 x i32> inreg %rsrc, i32 addrspace(1)* inreg %out, i32 %s, i32 %t, i32 %fragid) {
|
||||
@ -244,7 +260,8 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_2darraymsaa:
|
||||
; GCN: image_load v[0:3], v[0:3], s[0:7] dmask:0xf unorm da{{$}}
|
||||
; GFX6789: image_load v[0:3], v[0:3], s[0:7] dmask:0xf unorm da{{$}}
|
||||
; GFX10: image_load v[0:3], v[0:3], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm ;
|
||||
define amdgpu_ps <4 x float> @load_2darraymsaa(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %slice, i32 %fragid) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.load.2darraymsaa.v4f32.i32(i32 15, i32 %s, i32 %t, i32 %slice, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
@ -262,7 +279,8 @@ main_body:
|
||||
; NOPRT-NOT: v_mov_b32_e32 v1
|
||||
; NOPRT-NOT: v_mov_b32_e32 v2
|
||||
; NOPRT-NOT: v_mov_b32_e32 v3
|
||||
; GCN: image_load v[0:4], v[{{[0-9]+:[0-9]+}}], s[0:7] dmask:0xf unorm tfe da{{$}}
|
||||
; GFX6789: image_load v[0:4], v[{{[0-9]+:[0-9]+}}], s[0:7] dmask:0xf unorm tfe da{{$}}
|
||||
; GFX10: image_load v[0:4], v[{{[0-9]+:[0-9]+}}], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm tfe ;
|
||||
; SIVI: buffer_store_dword v4, off, s[8:11], 0
|
||||
; GFX900: global_store_dword v[{{[0-9]+:[0-9]+}}], v4
|
||||
define amdgpu_ps <4 x float> @load_2darraymsaa_tfe(<8 x i32> inreg %rsrc, i32 addrspace(1)* inreg %out, i32 %s, i32 %t, i32 %slice, i32 %fragid) {
|
||||
@ -275,7 +293,8 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_mip_1d:
|
||||
; GCN: image_load_mip v[0:3], v[0:1], s[0:7] dmask:0xf unorm{{$}}
|
||||
; GFX6789: image_load_mip v[0:3], v[0:1], s[0:7] dmask:0xf unorm{{$}}
|
||||
; GFX10: image_load_mip v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm ;
|
||||
define amdgpu_ps <4 x float> @load_mip_1d(<8 x i32> inreg %rsrc, i32 %s, i32 %mip) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.load.mip.1d.v4f32.i32(i32 15, i32 %s, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
@ -293,7 +312,8 @@ main_body:
|
||||
; NOPRT-NOT: v_mov_b32_e32 v1
|
||||
; NOPRT-NOT: v_mov_b32_e32 v2
|
||||
; NOPRT-NOT: v_mov_b32_e32 v3
|
||||
; GCN: image_load_mip v[0:4], v[{{[0-9]+:[0-9]+}}], s[0:7] dmask:0xf unorm lwe{{$}}
|
||||
; GFX6789: image_load_mip v[0:4], v[{{[0-9]+:[0-9]+}}], s[0:7] dmask:0xf unorm lwe{{$}}
|
||||
; GFX10: image_load_mip v[0:4], v[{{[0-9]+:[0-9]+}}], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm lwe ;
|
||||
; SIVI: buffer_store_dword v4, off, s[8:11], 0
|
||||
; GFX900: global_store_dword v[{{[0-9]+:[0-9]+}}], v4
|
||||
define amdgpu_ps <4 x float> @load_mip_1d_lwe(<8 x i32> inreg %rsrc, i32 addrspace(1)* inreg %out, i32 %s, i32 %mip) {
|
||||
@ -306,7 +326,8 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_mip_2d:
|
||||
; GCN: image_load_mip v[0:3], v[0:3], s[0:7] dmask:0xf unorm{{$}}
|
||||
; GFX6789: image_load_mip v[0:3], v[0:3], s[0:7] dmask:0xf unorm{{$}}
|
||||
; GFX10: image_load_mip v[0:3], v[0:2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm ;
|
||||
define amdgpu_ps <4 x float> @load_mip_2d(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %mip) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i32(i32 15, i32 %s, i32 %t, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
@ -324,7 +345,8 @@ main_body:
|
||||
; NOPRT-NOT: v_mov_b32_e32 v1
|
||||
; NOPRT-NOT: v_mov_b32_e32 v2
|
||||
; NOPRT-NOT: v_mov_b32_e32 v3
|
||||
; GCN: image_load_mip v[0:4], v[{{[0-9]+:[0-9]+}}], s[0:7] dmask:0xf unorm tfe{{$}}
|
||||
; GFX6789: image_load_mip v[0:4], v[{{[0-9]+:[0-9]+}}], s[0:7] dmask:0xf unorm tfe{{$}}
|
||||
; GFX10: image_load_mip v[0:4], v[{{[0-9]+:[0-9]+}}], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm tfe ;
|
||||
; SIVI: buffer_store_dword v4, off, s[8:11], 0
|
||||
; GFX900: global_store_dword v[{{[0-9]+:[0-9]+}}], v4
|
||||
define amdgpu_ps <4 x float> @load_mip_2d_tfe(<8 x i32> inreg %rsrc, i32 addrspace(1)* inreg %out, i32 %s, i32 %t, i32 %mip) {
|
||||
@ -432,7 +454,8 @@ main_body:
|
||||
; NOPRT-NOT: v_mov_b32_e32 v0
|
||||
; NOPRT-NOT: v_mov_b32_e32 v1
|
||||
; NOPRT-NOT: v_mov_b32_e32 v2
|
||||
; GCN: image_load v[0:3], v{{[0-9]+}}, s[0:7] dmask:0x7 unorm tfe{{$}}
|
||||
; GFX6789: image_load v[0:3], v{{[0-9]+}}, s[0:7] dmask:0x7 unorm tfe{{$}}
|
||||
; GFX10: image_load v[0:3], v{{[0-9]+}}, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_1D unorm tfe ;
|
||||
; SIVI: buffer_store_dword v3, off, s[8:11], 0
|
||||
; GFX900: global_store_dword v[{{[0-9]+:[0-9]+}}], v3
|
||||
define amdgpu_ps <4 x float> @load_1d_tfe_V4_dmask3(<8 x i32> inreg %rsrc, i32 addrspace(1)* inreg %out, i32 %s) {
|
||||
@ -451,7 +474,8 @@ main_body:
|
||||
; NOPRT: v_mov_b32_e32 v2, 0
|
||||
; NOPRT-NOT: v_mov_b32_e32 v0
|
||||
; NOPRT-NOT: v_mov_b32_e32 v1
|
||||
; GCN: image_load v[0:2], v{{[0-9]+}}, s[0:7] dmask:0x6 unorm tfe{{$}}
|
||||
; GFX6789: image_load v[0:2], v{{[0-9]+}}, s[0:7] dmask:0x6 unorm tfe{{$}}
|
||||
; GFX10: image_load v[0:2], v{{[0-9]+}}, s[0:7] dmask:0x6 dim:SQ_RSRC_IMG_1D unorm tfe ;
|
||||
; SIVI: buffer_store_dword v2, off, s[8:11], 0
|
||||
; GFX900: global_store_dword v[{{[0-9]+:[0-9]+}}], v2
|
||||
define amdgpu_ps <4 x float> @load_1d_tfe_V4_dmask2(<8 x i32> inreg %rsrc, i32 addrspace(1)* inreg %out, i32 %s) {
|
||||
@ -468,7 +492,8 @@ main_body:
|
||||
; PRT-DAG: v_mov_b32_e32 v{{[0-9]+}}, v0
|
||||
; NOPRT: v_mov_b32_e32 v1, 0
|
||||
; NOPRT-NOT: v_mov_b32_e32 v0
|
||||
; GCN: image_load v[0:1], v{{[0-9]+}}, s[0:7] dmask:0x8 unorm tfe{{$}}
|
||||
; GFX6789: image_load v[0:1], v{{[0-9]+}}, s[0:7] dmask:0x8 unorm tfe{{$}}
|
||||
; GFX10: image_load v[0:1], v{{[0-9]+}}, s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_1D unorm tfe ;
|
||||
; SIVI: buffer_store_dword v1, off, s[8:11], 0
|
||||
; GFX900: global_store_dword v[{{[0-9]+:[0-9]+}}], v1
|
||||
define amdgpu_ps <4 x float> @load_1d_tfe_V4_dmask1(<8 x i32> inreg %rsrc, i32 addrspace(1)* inreg %out, i32 %s) {
|
||||
@ -485,7 +510,8 @@ main_body:
|
||||
; PRT-DAG: v_mov_b32_e32 v{{[0-9]+}}, v0
|
||||
; NOPRT: v_mov_b32_e32 v1, 0
|
||||
; NOPRT-NOT: v_mov_b32_e32 v0
|
||||
; GCN: image_load v[0:1], v{{[0-9]+}}, s[0:7] dmask:0x8 unorm tfe{{$}}
|
||||
; GFX6789: image_load v[0:1], v{{[0-9]+}}, s[0:7] dmask:0x8 unorm tfe{{$}}
|
||||
; GFX10: image_load v[0:1], v{{[0-9]+}}, s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_1D unorm tfe ;
|
||||
; SIVI: buffer_store_dword v1, off, s[8:11], 0
|
||||
; GFX900: global_store_dword v[{{[0-9]+:[0-9]+}}], v1
|
||||
define amdgpu_ps <2 x float> @load_1d_tfe_V2_dmask1(<8 x i32> inreg %rsrc, i32 addrspace(1)* inreg %out, i32 %s) {
|
||||
@ -499,7 +525,8 @@ main_body:
|
||||
|
||||
|
||||
; GCN-LABEL: {{^}}load_mip_3d:
|
||||
; GCN: image_load_mip v[0:3], v[0:3], s[0:7] dmask:0xf unorm{{$}}
|
||||
; GFX6789: image_load_mip v[0:3], v[0:3], s[0:7] dmask:0xf unorm{{$}}
|
||||
; GFX10: image_load_mip v[0:3], v[0:3], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm ;
|
||||
define amdgpu_ps <4 x float> @load_mip_3d(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %r, i32 %mip) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.load.mip.3d.v4f32.i32(i32 15, i32 %s, i32 %t, i32 %r, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
@ -507,7 +534,8 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_mip_cube:
|
||||
; GCN: image_load_mip v[0:3], v[0:3], s[0:7] dmask:0xf unorm da{{$}}
|
||||
; GFX6789: image_load_mip v[0:3], v[0:3], s[0:7] dmask:0xf unorm da{{$}}
|
||||
; GFX10: image_load_mip v[0:3], v[0:3], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE unorm ;
|
||||
define amdgpu_ps <4 x float> @load_mip_cube(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %slice, i32 %mip) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.load.mip.cube.v4f32.i32(i32 15, i32 %s, i32 %t, i32 %slice, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
@ -515,7 +543,8 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_mip_1darray:
|
||||
; GCN: image_load_mip v[0:3], v[0:3], s[0:7] dmask:0xf unorm da{{$}}
|
||||
; GFX6789: image_load_mip v[0:3], v[0:3], s[0:7] dmask:0xf unorm da{{$}}
|
||||
; GFX10: image_load_mip v[0:3], v[0:2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY unorm ;
|
||||
define amdgpu_ps <4 x float> @load_mip_1darray(<8 x i32> inreg %rsrc, i32 %s, i32 %slice, i32 %mip) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.load.mip.1darray.v4f32.i32(i32 15, i32 %s, i32 %slice, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
@ -523,7 +552,8 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_mip_2darray:
|
||||
; GCN: image_load_mip v[0:3], v[0:3], s[0:7] dmask:0xf unorm da{{$}}
|
||||
; GFX6789: image_load_mip v[0:3], v[0:3], s[0:7] dmask:0xf unorm da{{$}}
|
||||
; GFX10: image_load_mip v[0:3], v[0:3], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY unorm ;
|
||||
define amdgpu_ps <4 x float> @load_mip_2darray(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %slice, i32 %mip) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.load.mip.2darray.v4f32.i32(i32 15, i32 %s, i32 %t, i32 %slice, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
@ -531,7 +561,8 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store_1d:
|
||||
; GCN: image_store v[0:3], v4, s[0:7] dmask:0xf unorm{{$}}
|
||||
; GFX6789: image_store v[0:3], v4, s[0:7] dmask:0xf unorm{{$}}
|
||||
; GFX10: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm ;
|
||||
define amdgpu_ps void @store_1d(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s) {
|
||||
main_body:
|
||||
call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
@ -539,7 +570,8 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store_2d:
|
||||
; GCN: image_store v[0:3], v[4:5], s[0:7] dmask:0xf unorm{{$}}
|
||||
; GFX6789: image_store v[0:3], v[4:5], s[0:7] dmask:0xf unorm{{$}}
|
||||
; GFX10: image_store v[0:3], v[4:5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm ;
|
||||
define amdgpu_ps void @store_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t) {
|
||||
main_body:
|
||||
call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
@ -547,7 +579,8 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store_3d:
|
||||
; GCN: image_store v[0:3], v[4:7], s[0:7] dmask:0xf unorm{{$}}
|
||||
; GFX6789: image_store v[0:3], v[4:7], s[0:7] dmask:0xf unorm{{$}}
|
||||
; GFX10: image_store v[0:3], v[4:6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm ;
|
||||
define amdgpu_ps void @store_3d(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t, i32 %r) {
|
||||
main_body:
|
||||
call void @llvm.amdgcn.image.store.3d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 %r, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
@ -555,7 +588,8 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store_cube:
|
||||
; GCN: image_store v[0:3], v[4:7], s[0:7] dmask:0xf unorm da{{$}}
|
||||
; GFX6789: image_store v[0:3], v[4:7], s[0:7] dmask:0xf unorm da{{$}}
|
||||
; GFX10: image_store v[0:3], v[4:6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE unorm ;
|
||||
define amdgpu_ps void @store_cube(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t, i32 %slice) {
|
||||
main_body:
|
||||
call void @llvm.amdgcn.image.store.cube.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 %slice, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
@ -563,7 +597,8 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store_1darray:
|
||||
; GCN: image_store v[0:3], v[4:5], s[0:7] dmask:0xf unorm da{{$}}
|
||||
; GFX6789: image_store v[0:3], v[4:5], s[0:7] dmask:0xf unorm da{{$}}
|
||||
; GFX10: image_store v[0:3], v[4:5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY unorm ;
|
||||
define amdgpu_ps void @store_1darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %slice) {
|
||||
main_body:
|
||||
call void @llvm.amdgcn.image.store.1darray.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %slice, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
@ -571,7 +606,8 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store_2darray:
|
||||
; GCN: image_store v[0:3], v[4:7], s[0:7] dmask:0xf unorm da{{$}}
|
||||
; GFX6789: image_store v[0:3], v[4:7], s[0:7] dmask:0xf unorm da{{$}}
|
||||
; GFX10: image_store v[0:3], v[4:6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY unorm ;
|
||||
define amdgpu_ps void @store_2darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t, i32 %slice) {
|
||||
main_body:
|
||||
call void @llvm.amdgcn.image.store.2darray.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 %slice, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
@ -579,7 +615,8 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store_2dmsaa:
|
||||
; GCN: image_store v[0:3], v[4:7], s[0:7] dmask:0xf unorm{{$}}
|
||||
; GFX6789: image_store v[0:3], v[4:7], s[0:7] dmask:0xf unorm{{$}}
|
||||
; GFX10: image_store v[0:3], v[4:6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA unorm ;
|
||||
define amdgpu_ps void @store_2dmsaa(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t, i32 %fragid) {
|
||||
main_body:
|
||||
call void @llvm.amdgcn.image.store.2dmsaa.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
@ -587,7 +624,8 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store_2darraymsaa:
|
||||
; GCN: image_store v[0:3], v[4:7], s[0:7] dmask:0xf unorm da{{$}}
|
||||
; GFX6789: image_store v[0:3], v[4:7], s[0:7] dmask:0xf unorm da{{$}}
|
||||
; GFX10: image_store v[0:3], v[4:7], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm ;
|
||||
define amdgpu_ps void @store_2darraymsaa(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t, i32 %slice, i32 %fragid) {
|
||||
main_body:
|
||||
call void @llvm.amdgcn.image.store.2darraymsaa.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 %slice, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
@ -595,7 +633,8 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store_mip_1d:
|
||||
; GCN: image_store_mip v[0:3], v[4:5], s[0:7] dmask:0xf unorm{{$}}
|
||||
; GFX6789: image_store_mip v[0:3], v[4:5], s[0:7] dmask:0xf unorm{{$}}
|
||||
; GFX10: image_store_mip v[0:3], v[4:5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm ;
|
||||
define amdgpu_ps void @store_mip_1d(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %mip) {
|
||||
main_body:
|
||||
call void @llvm.amdgcn.image.store.mip.1d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
@ -603,7 +642,8 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store_mip_2d:
|
||||
; GCN: image_store_mip v[0:3], v[4:7], s[0:7] dmask:0xf unorm{{$}}
|
||||
; GFX6789: image_store_mip v[0:3], v[4:7], s[0:7] dmask:0xf unorm{{$}}
|
||||
; GFX10: image_store_mip v[0:3], v[4:6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm ;
|
||||
define amdgpu_ps void @store_mip_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t, i32 %mip) {
|
||||
main_body:
|
||||
call void @llvm.amdgcn.image.store.mip.2d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
@ -611,7 +651,8 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store_mip_3d:
|
||||
; GCN: image_store_mip v[0:3], v[4:7], s[0:7] dmask:0xf unorm{{$}}
|
||||
; GFX6789: image_store_mip v[0:3], v[4:7], s[0:7] dmask:0xf unorm{{$}}
|
||||
; GFX10: image_store_mip v[0:3], v[4:7], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm ;
|
||||
define amdgpu_ps void @store_mip_3d(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t, i32 %r, i32 %mip) {
|
||||
main_body:
|
||||
call void @llvm.amdgcn.image.store.mip.3d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 %r, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
@ -619,7 +660,8 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store_mip_cube:
|
||||
; GCN: image_store_mip v[0:3], v[4:7], s[0:7] dmask:0xf unorm da{{$}}
|
||||
; GFX6789: image_store_mip v[0:3], v[4:7], s[0:7] dmask:0xf unorm da{{$}}
|
||||
; GFX10: image_store_mip v[0:3], v[4:7], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE unorm ;
|
||||
define amdgpu_ps void @store_mip_cube(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t, i32 %slice, i32 %mip) {
|
||||
main_body:
|
||||
call void @llvm.amdgcn.image.store.mip.cube.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 %slice, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
@ -627,7 +669,8 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store_mip_1darray:
|
||||
; GCN: image_store_mip v[0:3], v[4:7], s[0:7] dmask:0xf unorm da{{$}}
|
||||
; GFX6789: image_store_mip v[0:3], v[4:7], s[0:7] dmask:0xf unorm da{{$}}
|
||||
; GFX10: image_store_mip v[0:3], v[4:6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY unorm ;
|
||||
define amdgpu_ps void @store_mip_1darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %slice, i32 %mip) {
|
||||
main_body:
|
||||
call void @llvm.amdgcn.image.store.mip.1darray.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %slice, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
@ -635,7 +678,8 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store_mip_2darray:
|
||||
; GCN: image_store_mip v[0:3], v[4:7], s[0:7] dmask:0xf unorm da{{$}}
|
||||
; GFX6789: image_store_mip v[0:3], v[4:7], s[0:7] dmask:0xf unorm da{{$}}
|
||||
; GFX10: image_store_mip v[0:3], v[4:7], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY unorm ;
|
||||
define amdgpu_ps void @store_mip_2darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t, i32 %slice, i32 %mip) {
|
||||
main_body:
|
||||
call void @llvm.amdgcn.image.store.mip.2darray.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 %slice, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
@ -643,7 +687,8 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}getresinfo_1d:
|
||||
; GCN: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm{{$}}
|
||||
; GFX6789: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm{{$}}
|
||||
; GFX10: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm ;
|
||||
define amdgpu_ps <4 x float> @getresinfo_1d(<8 x i32> inreg %rsrc, i32 %mip) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.1d.v4f32.i32(i32 15, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
@ -651,7 +696,8 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}getresinfo_2d:
|
||||
; GCN: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm{{$}}
|
||||
; GFX6789: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm{{$}}
|
||||
; GFX10: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm ;
|
||||
define amdgpu_ps <4 x float> @getresinfo_2d(<8 x i32> inreg %rsrc, i32 %mip) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.2d.v4f32.i32(i32 15, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
@ -659,7 +705,8 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}getresinfo_3d:
|
||||
; GCN: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm{{$}}
|
||||
; GFX6789: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm{{$}}
|
||||
; GFX10: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm ;
|
||||
define amdgpu_ps <4 x float> @getresinfo_3d(<8 x i32> inreg %rsrc, i32 %mip) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.3d.v4f32.i32(i32 15, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
@ -667,7 +714,8 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}getresinfo_cube:
|
||||
; GCN: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm da{{$}}
|
||||
; GFX6789: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm da{{$}}
|
||||
; GFX10: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE unorm ;
|
||||
define amdgpu_ps <4 x float> @getresinfo_cube(<8 x i32> inreg %rsrc, i32 %mip) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.cube.v4f32.i32(i32 15, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
@ -675,7 +723,8 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}getresinfo_1darray:
|
||||
; GCN: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm da{{$}}
|
||||
; GFX6789: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm da{{$}}
|
||||
; GFX10: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY unorm ;
|
||||
define amdgpu_ps <4 x float> @getresinfo_1darray(<8 x i32> inreg %rsrc, i32 %mip) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.1darray.v4f32.i32(i32 15, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
@ -683,7 +732,8 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}getresinfo_2darray:
|
||||
; GCN: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm da{{$}}
|
||||
; GFX6789: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm da{{$}}
|
||||
; GFX10: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY unorm ;
|
||||
define amdgpu_ps <4 x float> @getresinfo_2darray(<8 x i32> inreg %rsrc, i32 %mip) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.2darray.v4f32.i32(i32 15, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
@ -691,7 +741,8 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}getresinfo_2dmsaa:
|
||||
; GCN: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm{{$}}
|
||||
; GFX6789: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm{{$}}
|
||||
; GFX10: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA unorm ;
|
||||
define amdgpu_ps <4 x float> @getresinfo_2dmsaa(<8 x i32> inreg %rsrc, i32 %mip) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.2dmsaa.v4f32.i32(i32 15, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
@ -699,7 +750,8 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}getresinfo_2darraymsaa:
|
||||
; GCN: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm da{{$}}
|
||||
; GFX6789: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm da{{$}}
|
||||
; GFX10: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm ;
|
||||
define amdgpu_ps <4 x float> @getresinfo_2darraymsaa(<8 x i32> inreg %rsrc, i32 %mip) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.2darraymsaa.v4f32.i32(i32 15, i32 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
@ -707,7 +759,8 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_1d_V1:
|
||||
; GCN: image_load v0, v0, s[0:7] dmask:0x8 unorm{{$}}
|
||||
; GFX6789: image_load v0, v0, s[0:7] dmask:0x8 unorm{{$}}
|
||||
; GFX10: image_load v0, v0, s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_1D unorm ;
|
||||
define amdgpu_ps float @load_1d_V1(<8 x i32> inreg %rsrc, i32 %s) {
|
||||
main_body:
|
||||
%v = call float @llvm.amdgcn.image.load.1d.f32.i32(i32 8, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
@ -715,7 +768,8 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_1d_V2:
|
||||
; GCN: image_load v[0:1], v0, s[0:7] dmask:0x9 unorm{{$}}
|
||||
; GFX6789: image_load v[0:1], v0, s[0:7] dmask:0x9 unorm{{$}}
|
||||
; GFX10: image_load v[0:1], v0, s[0:7] dmask:0x9 dim:SQ_RSRC_IMG_1D unorm ;
|
||||
define amdgpu_ps <2 x float> @load_1d_V2(<8 x i32> inreg %rsrc, i32 %s) {
|
||||
main_body:
|
||||
%v = call <2 x float> @llvm.amdgcn.image.load.1d.v2f32.i32(i32 9, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
@ -723,7 +777,8 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store_1d_V1:
|
||||
; GCN: image_store v0, v1, s[0:7] dmask:0x2 unorm{{$}}
|
||||
; GFX6789: image_store v0, v1, s[0:7] dmask:0x2 unorm{{$}}
|
||||
; GFX10: image_store v0, v1, s[0:7] dmask:0x2 dim:SQ_RSRC_IMG_1D unorm ;
|
||||
define amdgpu_ps void @store_1d_V1(<8 x i32> inreg %rsrc, float %vdata, i32 %s) {
|
||||
main_body:
|
||||
call void @llvm.amdgcn.image.store.1d.f32.i32(float %vdata, i32 2, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
@ -731,7 +786,8 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store_1d_V2:
|
||||
; GCN: image_store v[0:1], v2, s[0:7] dmask:0xc unorm{{$}}
|
||||
; GFX6789: image_store v[0:1], v2, s[0:7] dmask:0xc unorm{{$}}
|
||||
; GFX10: image_store v[0:1], v2, s[0:7] dmask:0xc dim:SQ_RSRC_IMG_1D unorm ;
|
||||
define amdgpu_ps void @store_1d_V2(<8 x i32> inreg %rsrc, <2 x float> %vdata, i32 %s) {
|
||||
main_body:
|
||||
call void @llvm.amdgcn.image.store.1d.v2f32.i32(<2 x float> %vdata, i32 12, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
@ -739,7 +795,8 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_1d_glc:
|
||||
; GCN: image_load v[0:3], v0, s[0:7] dmask:0xf unorm glc{{$}}
|
||||
; GFX6789: image_load v[0:3], v0, s[0:7] dmask:0xf unorm glc{{$}}
|
||||
; GFX10: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm glc ;
|
||||
define amdgpu_ps <4 x float> @load_1d_glc(<8 x i32> inreg %rsrc, i32 %s) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 1)
|
||||
@ -747,7 +804,8 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_1d_slc:
|
||||
; GCN: image_load v[0:3], v0, s[0:7] dmask:0xf unorm slc{{$}}
|
||||
; GFX6789: image_load v[0:3], v0, s[0:7] dmask:0xf unorm slc{{$}}
|
||||
; GFX10: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm slc ;
|
||||
define amdgpu_ps <4 x float> @load_1d_slc(<8 x i32> inreg %rsrc, i32 %s) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 2)
|
||||
@ -755,7 +813,8 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_1d_glc_slc:
|
||||
; GCN: image_load v[0:3], v0, s[0:7] dmask:0xf unorm glc slc{{$}}
|
||||
; GFX6789: image_load v[0:3], v0, s[0:7] dmask:0xf unorm glc slc{{$}}
|
||||
; GFX10: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm glc slc ;
|
||||
define amdgpu_ps <4 x float> @load_1d_glc_slc(<8 x i32> inreg %rsrc, i32 %s) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 3)
|
||||
@ -763,7 +822,8 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store_1d_glc:
|
||||
; GCN: image_store v[0:3], v4, s[0:7] dmask:0xf unorm glc{{$}}
|
||||
; GFX6789: image_store v[0:3], v4, s[0:7] dmask:0xf unorm glc{{$}}
|
||||
; GFX10: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm glc ;
|
||||
define amdgpu_ps void @store_1d_glc(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s) {
|
||||
main_body:
|
||||
call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 1)
|
||||
@ -771,7 +831,8 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store_1d_slc:
|
||||
; GCN: image_store v[0:3], v4, s[0:7] dmask:0xf unorm slc{{$}}
|
||||
; GFX6789: image_store v[0:3], v4, s[0:7] dmask:0xf unorm slc{{$}}
|
||||
; GFX10: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm slc ;
|
||||
define amdgpu_ps void @store_1d_slc(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s) {
|
||||
main_body:
|
||||
call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 2)
|
||||
@ -779,7 +840,8 @@ main_body:
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store_1d_glc_slc:
|
||||
; GCN: image_store v[0:3], v4, s[0:7] dmask:0xf unorm glc slc{{$}}
|
||||
; GFX6789: image_store v[0:3], v4, s[0:7] dmask:0xf unorm glc slc{{$}}
|
||||
; GFX10: image_store v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm glc slc ;
|
||||
define amdgpu_ps void @store_1d_glc_slc(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s) {
|
||||
main_body:
|
||||
call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 3)
|
||||
@ -798,11 +860,11 @@ main_body:
|
||||
; Ideally, the register allocator would avoid the wait here
|
||||
;
|
||||
; GCN-LABEL: {{^}}image_store_wait:
|
||||
; GCN: image_store v[0:3], v4, s[0:7] dmask:0xf unorm
|
||||
; GCN: image_store v[0:3], v4, s[0:7] dmask:0xf
|
||||
; SI: s_waitcnt expcnt(0)
|
||||
; GCN: image_load v[0:3], v4, s[8:15] dmask:0xf unorm
|
||||
; GCN: image_load v[0:3], v4, s[8:15] dmask:0xf
|
||||
; GCN: s_waitcnt vmcnt(0)
|
||||
; GCN: image_store v[0:3], v4, s[16:23] dmask:0xf unorm
|
||||
; GCN: image_store v[0:3], v4, s[16:23] dmask:0xf
|
||||
define amdgpu_ps void @image_store_wait(<8 x i32> inreg %arg, <8 x i32> inreg %arg1, <8 x i32> inreg %arg2, <4 x float> %arg3, i32 %arg4) #0 {
|
||||
main_body:
|
||||
call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %arg3, i32 15, i32 %arg4, <8 x i32> %arg, i32 0, i32 0)
|
||||
@ -812,10 +874,10 @@ main_body:
|
||||
}
|
||||
|
||||
; SI won't merge ds memory operations, because of the signed offset bug, so
|
||||
; we only have check lines for VI.
|
||||
; VI-LABEL: image_load_mmo
|
||||
; VI: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0
|
||||
; VI: ds_write2_b32 v{{[0-9]+}}, [[ZERO]], [[ZERO]] offset1:4
|
||||
; we only have check lines for VI+.
|
||||
; GFX8910-LABEL: image_load_mmo
|
||||
; GFX8910: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0
|
||||
; GFX8910: ds_write2_b32 v{{[0-9]+}}, [[ZERO]], [[ZERO]] offset1:4
|
||||
define amdgpu_ps float @image_load_mmo(<8 x i32> inreg %rsrc, float addrspace(3)* %lds, <2 x i32> %c) #0 {
|
||||
store float 0.000000e+00, float addrspace(3)* %lds
|
||||
%c0 = extractelement <2 x i32> %c, i32 0
|
||||
|
||||
102
test/CodeGen/AMDGPU/nsa-reassign.ll
Normal file
102
test/CodeGen/AMDGPU/nsa-reassign.ll
Normal file
@ -0,0 +1,102 @@
|
||||
; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
|
||||
|
||||
; GCN-LABEL: {{^}}sample_contig_nsa:
|
||||
; GCN-DAG: image_sample_c_l v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}],
|
||||
; GCN-DAG: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}],
|
||||
define amdgpu_ps <2 x float> @sample_contig_nsa(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s1, float %t1, float %r1, float %lod, float %r2, float %s2, float %t2) {
|
||||
main_body:
|
||||
%zcompare.1 = fadd float %zcompare, 1.0
|
||||
%s1.1 = fadd float %s1, 1.0
|
||||
%t1.1 = fadd float %t1, 1.0
|
||||
%r1.1 = fadd float %r1, 1.0
|
||||
%s2.1 = fadd float %s2, 1.0
|
||||
%t2.1 = fadd float %t2, 1.0
|
||||
%r2.1 = fadd float %r2, 1.0
|
||||
%lod.1 = fadd float %lod, 1.0
|
||||
%v1 = call float @llvm.amdgcn.image.sample.c.l.3d.f32.f32(i32 1, float %zcompare.1, float %s1.1, float %t1.1, float %r1.1, float %lod.1, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
%v2 = call float @llvm.amdgcn.image.sample.3d.f32.f32(i32 1, float %s2.1, float %t2.1, float %r2.1, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
%r.0 = insertelement <2 x float> undef, float %v1, i32 0
|
||||
%r = insertelement <2 x float> %r.0, float %v2, i32 1
|
||||
ret <2 x float> %r
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_contig_nsa_10vgprs:
|
||||
; GCN-DAG: image_sample_c_l v{{[0-9]+}}, [{{v[0-9]+, v[0-9]+, v[0-9]+, v[0-9]+, v[0-9]+}}],
|
||||
; GCN-DAG: image_sample v{{[0-9]+}}, [{{v[0-9]+, v[0-9]+, v[0-9]+}}],
|
||||
define amdgpu_ps <2 x float> @sample_contig_nsa_10vgprs(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s1, float %t1, float %r1, float %lod, float %r2, float %s2, float %t2) #0 {
|
||||
main_body:
|
||||
%zcompare.1 = fadd float %zcompare, 1.0
|
||||
%s1.1 = fadd float %s1, 1.0
|
||||
%t1.1 = fadd float %t1, 1.0
|
||||
%r1.1 = fadd float %r1, 1.0
|
||||
%s2.1 = fadd float %s2, 1.0
|
||||
%t2.1 = fadd float %t2, 1.0
|
||||
%r2.1 = fadd float %r2, 1.0
|
||||
%lod.1 = fadd float %lod, 1.0
|
||||
%v1 = call float @llvm.amdgcn.image.sample.c.l.3d.f32.f32(i32 1, float %zcompare.1, float %s1.1, float %t1.1, float %r1.1, float %lod.1, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
%v2 = call float @llvm.amdgcn.image.sample.3d.f32.f32(i32 1, float %s2.1, float %t2.1, float %r2.1, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
%r.0 = insertelement <2 x float> undef, float %v1, i32 0
|
||||
%r = insertelement <2 x float> %r.0, float %v2, i32 1
|
||||
ret <2 x float> %r
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_contig_nsa_conflict:
|
||||
; GCN-DAG: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}],
|
||||
; GCN-DAG: image_sample v{{[0-9]+}}, [{{v[0-9]+, v[0-9]+, v[0-9]+}}],
|
||||
define amdgpu_ps <2 x float> @sample_contig_nsa_conflict(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s1, float %t1, float %r1, float %lod, float %r2, float %s2, float %t2) {
|
||||
main_body:
|
||||
%zcompare.1 = fadd float %zcompare, 1.0
|
||||
%s1.1 = fadd float %s1, 1.0
|
||||
%t1.1 = fadd float %t1, 1.0
|
||||
%r1.1 = fadd float %r1, 1.0
|
||||
%s2.1 = fadd float %s2, 1.0
|
||||
%t2.1 = fadd float %t2, 1.0
|
||||
%r2.1 = fadd float %r2, 1.0
|
||||
%lod.1 = fadd float %lod, 1.0
|
||||
%v2 = call float @llvm.amdgcn.image.sample.3d.f32.f32(i32 1, float %s2.1, float %t2.1, float %r2.1, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
%v1 = call float @llvm.amdgcn.image.sample.3d.f32.f32(i32 1, float %t2.1, float %s2.1, float %r2.1, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
%r.0 = insertelement <2 x float> undef, float %v1, i32 0
|
||||
%r = insertelement <2 x float> %r.0, float %v2, i32 1
|
||||
ret <2 x float> %r
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_contig_nsa_same_addr:
|
||||
; GCN-DAG: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}],
|
||||
; GCN-DAG: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}],
|
||||
define amdgpu_ps <2 x float> @sample_contig_nsa_same_addr(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s1, float %t1, float %r1, float %lod, float %r2, float %s2, float %t2) {
|
||||
main_body:
|
||||
%zcompare.1 = fadd float %zcompare, 1.0
|
||||
%s1.1 = fadd float %s1, 1.0
|
||||
%t1.1 = fadd float %t1, 1.0
|
||||
%r1.1 = fadd float %r1, 1.0
|
||||
%s2.1 = fadd float %s2, 1.0
|
||||
%t2.1 = fadd float %t2, 1.0
|
||||
%r2.1 = fadd float %r2, 1.0
|
||||
%lod.1 = fadd float %lod, 1.0
|
||||
%v2 = call float @llvm.amdgcn.image.sample.3d.f32.f32(i32 1, float %s2.1, float %t2.1, float %r2.1, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 1)
|
||||
%v1 = call float @llvm.amdgcn.image.sample.3d.f32.f32(i32 1, float %s2.1, float %t2.1, float %r2.1, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
%r.0 = insertelement <2 x float> undef, float %v1, i32 0
|
||||
%r = insertelement <2 x float> %r.0, float %v2, i32 1
|
||||
ret <2 x float> %r
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_contig_nsa_same_reg:
|
||||
; GCN-DAG: image_sample v{{[0-9]+}}, [{{v[0-9]+, v[0-9]+, v[0-9]+}}],
|
||||
define amdgpu_ps float @sample_contig_nsa_same_reg(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s1, float %t1, float %r1, float %lod, float %r2, float %s2, float %t2) {
|
||||
main_body:
|
||||
%zcompare.1 = fadd float %zcompare, 1.0
|
||||
%s1.1 = fadd float %s1, 1.0
|
||||
%t1.1 = fadd float %t1, 1.0
|
||||
%r1.1 = fadd float %r1, 1.0
|
||||
%s2.1 = fadd float %s2, 1.0
|
||||
%t2.1 = fadd float %t2, 1.0
|
||||
%r2.1 = fadd float %r2, 1.0
|
||||
%lod.1 = fadd float %lod, 1.0
|
||||
%v = call float @llvm.amdgcn.image.sample.3d.f32.f32(i32 1, float %t2.1, float %t2.1, float %r2.1, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
ret float %v
|
||||
}
|
||||
|
||||
declare float @llvm.amdgcn.image.sample.3d.f32.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32)
|
||||
declare float @llvm.amdgcn.image.sample.c.l.3d.f32.f32(i32, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32)
|
||||
|
||||
attributes #0 = {"amdgpu-num-vgpr"="10"}
|
||||
Loading…
Reference in New Issue
Block a user