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Fix construction of ioport intrinsics, fixing X86/io.llx and io-port.llx

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22026 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-05-14 13:56:55 +00:00
parent 65af1abd1e
commit 1ca85d567c
1 changed files with 10 additions and 4 deletions
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14
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
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@ -711,14 +711,20 @@ void SelectionDAGLowering::visitCall(CallInst &I) {
case Intrinsic::memmove: visitMemIntrinsic(I, ISD::MEMMOVE); return;
case Intrinsic::readport:
case Intrinsic::readio:
case Intrinsic::readio: {
std::vector<MVT::ValueType> VTs;
VTs.push_back(TLI.getValueType(I.getType()));
VTs.push_back(MVT::Other);
std::vector<SDOperand> Ops;
Ops.push_back(getRoot());
Ops.push_back(getValue(I.getOperand(1)));
Tmp = DAG.getNode(F->getIntrinsicID() == Intrinsic::readport ?
ISD::READPORT : ISD::READIO,
TLI.getValueType(I.getType()), getRoot(),
getValue(I.getOperand(1)));
ISD::READPORT : ISD::READIO, VTs, Ops);
setValue(&I, Tmp);
DAG.setRoot(Tmp.getValue(1));
return;
}
case Intrinsic::writeport:
case Intrinsic::writeio:
DAG.setRoot(DAG.getNode(F->getIntrinsicID() == Intrinsic::writeport ?