diff --git a/include/llvm/IR/IntrinsicsARM.td b/include/llvm/IR/IntrinsicsARM.td index 09959859688..3240f49b2fd 100644 --- a/include/llvm/IR/IntrinsicsARM.td +++ b/include/llvm/IR/IntrinsicsARM.td @@ -123,15 +123,12 @@ def int_arm_cdp2 : GCCBuiltin<"__builtin_arm_cdp2">, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>; // Move from two registers to coprocessor -def int_arm_mcrr : Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, - llvm_i32_ty, llvm_i32_ty], []>; -def int_arm_mcrr2 : Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, - llvm_i32_ty, llvm_i32_ty], []>; - -def int_arm_mrrc : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_i32_ty, - llvm_i32_ty, llvm_i32_ty], []>; -def int_arm_mrrc2 : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_i32_ty, - llvm_i32_ty, llvm_i32_ty], []>; +def int_arm_mcrr : GCCBuiltin<"__builtin_arm_mcrr">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, + llvm_i32_ty, llvm_i32_ty], []>; +def int_arm_mcrr2 : GCCBuiltin<"__builtin_arm_mcrr2">, + Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, + llvm_i32_ty, llvm_i32_ty], []>; //===----------------------------------------------------------------------===// // CRC32 diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp index 74ce939ffd4..061c4b79266 100644 --- a/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -3335,34 +3335,6 @@ void ARMDAGToDAGISel::Select(SDNode *N) { default: break; - case Intrinsic::arm_mrrc: - case Intrinsic::arm_mrrc2: { - SDLoc dl(N); - SDValue Chain = N->getOperand(0); - unsigned Opc; - - if (Subtarget->isThumb()) - Opc = (IntNo == Intrinsic::arm_mrrc ? ARM::t2MRRC : ARM::t2MRRC2); - else - Opc = (IntNo == Intrinsic::arm_mrrc ? ARM::MRRC : ARM::MRRC2); - - SmallVector Ops; - Ops.push_back(getI32Imm(cast(N->getOperand(2))->getZExtValue(), dl)); /* coproc */ - Ops.push_back(getI32Imm(cast(N->getOperand(3))->getZExtValue(), dl)); /* opc */ - Ops.push_back(getI32Imm(cast(N->getOperand(4))->getZExtValue(), dl)); /* CRm */ - Ops.push_back(getAL(CurDAG, dl)); - Ops.push_back(CurDAG->getRegister(0, MVT::i32)); - Ops.push_back(Chain); - - // Writes to two registers. - std::vector RetType; - RetType.push_back(MVT::i32); - RetType.push_back(MVT::i32); - RetType.push_back(MVT::Other); - - ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, RetType, Ops)); - return; - } case Intrinsic::arm_ldaexd: case Intrinsic::arm_ldrexd: { SDLoc dl(N); diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index fa18ecd2764..37db70dfbbb 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -5145,9 +5145,9 @@ def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */, (outs GPRnopc:$Rt, GPRnopc:$Rt2), (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm), []>; -class MovRRCopro2 pattern = []> - : ABXI<0b1100, oops, iops, NoItinerary, +class MovRRCopro2 pattern = []> + : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1, + GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary, !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern>, Requires<[PreV8]> { let Inst{31-28} = 0b1111; @@ -5166,18 +5166,13 @@ class MovRRCopro2; - -def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */, - (outs GPRnopc:$Rt, GPRnopc:$Rt2), - (ins p_imm:$cop, imm0_15:$opc1, c_imm:$CRm), []>; +def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>; //===----------------------------------------------------------------------===// // Move between special register and ARM core register diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 3196a57ccc3..ad1e03ae1e7 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -395,8 +395,8 @@ static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); -static DecodeStatus DecoderForMRRC2AndMCRR2(llvm::MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder); +static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, + uint64_t Address, const void *Decoder); #include "ARMGenDisassemblerTables.inc" static MCDisassembler *createARMDisassembler(const Target &T, @@ -5265,8 +5265,8 @@ static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, return S; } -static DecodeStatus DecoderForMRRC2AndMCRR2(llvm::MCInst &Inst, unsigned Val, - uint64_t Address, const void *Decoder) { +static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, + uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler::Success; @@ -5282,30 +5282,12 @@ static DecodeStatus DecoderForMRRC2AndMCRR2(llvm::MCInst &Inst, unsigned Val, if (Rt == Rt2) S = MCDisassembler::SoftFail; - // We have to check if the instruction is MRRC2 - // or MCRR2 when constructing the operands for - // Inst. Reason is because MRRC2 stores to two - // registers so it's tablegen desc has has two - // outputs whereas MCRR doesn't store to any - // registers so all of it's operands are listed - // as inputs, therefore the operand order for - // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] - // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] - - if (Inst.getOpcode() == ARM::MRRC2) { - if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) - return MCDisassembler::Fail; - if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) - return MCDisassembler::Fail; - } Inst.addOperand(MCOperand::createImm(cop)); Inst.addOperand(MCOperand::createImm(opc1)); - if (Inst.getOpcode() == ARM::MCRR2) { - if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) - return MCDisassembler::Fail; - if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) - return MCDisassembler::Fail; - } + if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) + return MCDisassembler::Fail; Inst.addOperand(MCOperand::createImm(CRm)); return S; diff --git a/test/CodeGen/ARM/intrinsics-coprocessor.ll b/test/CodeGen/ARM/intrinsics-coprocessor.ll index 8fea49b39fb..ccaf5c29fad 100644 --- a/test/CodeGen/ARM/intrinsics-coprocessor.ll +++ b/test/CodeGen/ARM/intrinsics-coprocessor.ll @@ -35,10 +35,6 @@ entry: tail call void @llvm.arm.stc2(i32 7, i32 3, i8* %i) nounwind ; CHECK: stc2l p7, c3, [r{{[0-9]+}}] tail call void @llvm.arm.stc2l(i32 7, i32 3, i8* %i) nounwind - ; CHECK: mrrc p1, #2, r{{[0-9]+}}, r{{[0-9]+}}, c3 - %2 = tail call { i32, i32 } @llvm.arm.mrrc(i32 1, i32 2, i32 3) nounwind - ; CHECK: mrrc2 p1, #2, r{{[0-9]+}}, r{{[0-9]+}}, c3 - %3 = tail call { i32, i32 } @llvm.arm.mrrc2(i32 1, i32 2, i32 3) nounwind ret void } @@ -73,7 +69,3 @@ declare i32 @llvm.arm.mrc2(i32, i32, i32, i32, i32) nounwind declare void @llvm.arm.mcr(i32, i32, i32, i32, i32, i32) nounwind declare i32 @llvm.arm.mrc(i32, i32, i32, i32, i32) nounwind - -declare { i32, i32 } @llvm.arm.mrrc(i32, i32, i32) nounwind - -declare { i32, i32 } @llvm.arm.mrrc2(i32, i32, i32) nounwind