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Thumb2 assembly parsing for mul.w in IT block fix.

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When the 3rd operand is not a low-register, and the first two operands are
the same low register, the parser was incorrectly trying to use the 16-bit
instruction encoding.

rdar://10449281

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144679 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-11-15 19:29:45 +00:00
parent b5ccb25bc2
commit 1de0bd1945
2 changed files with 5 additions and 0 deletions
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1
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -4098,6 +4098,7 @@ bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
// remove the cc_out operand.
(!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
!isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
!isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
!inITBlock() ||
(static_cast<ARMOperand*>(Operands[3])->getReg() !=
static_cast<ARMOperand*>(Operands[5])->getReg() &&

4
test/MC/ARM/basic-thumb2-instructions.s
View File

@ -1228,12 +1228,16 @@ _func:
mul r3, r4, r6
it eq
muleq r3, r4, r5
it le
mulle r4, r4, r8
@ CHECK: muls r3, r4, r3 @ encoding: [0x63,0x43]
@ CHECK: mul r3, r4, r3 @ encoding: [0x04,0xfb,0x03,0xf3]
@ CHECK: mul r3, r4, r6 @ encoding: [0x04,0xfb,0x06,0xf3]
@ CHECK: it eq @ encoding: [0x08,0xbf]
@ CHECK: muleq r3, r4, r5 @ encoding: [0x04,0xfb,0x05,0xf3]
@ CHECK: it le @ encoding: [0xd8,0xbf]
@ CHECK: mulle r4, r4, r8 @ encoding: [0x04,0xfb,0x08,0xf4]
@------------------------------------------------------------------------------