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[X86] Don't let LowerEXTRACT_SUBVECTOR call getNode for EXTRACT_SUBVECTOR.

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This results in the simplifications inside of getNode running while we're legalizing nodes popped off the worklist during the final DAG combine. This basically makes a DAG combine like operation occur during this legalize step, but we don't handle something quite the same way. I think we don't recursively added the removed nodes to the DAG combiner worklist.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294929 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2017-02-12 23:49:46 +00:00
parent 583dfa966f
commit 1e59ad7d60
1 changed files with 7 additions and 5 deletions
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12
lib/Target/X86/X86ISelLowering.cpp
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@ -14010,12 +14010,14 @@ static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget &Subtarget,
In.getSimpleValueType().is512BitVector()) &&
"Can only extract from 256-bit or 512-bit vectors");
if (ResVT.is128BitVector())
return extract128BitVector(In, IdxVal, DAG, dl);
if (ResVT.is256BitVector())
return extract256BitVector(In, IdxVal, DAG, dl);
// If the input is a buildvector just emit a smaller one.
unsigned ElemsPerChunk = ResVT.getVectorNumElements();
if (In.getOpcode() == ISD::BUILD_VECTOR)
return DAG.getNode(ISD::BUILD_VECTOR, dl, ResVT,
makeArrayRef(In->op_begin() + IdxVal, ElemsPerChunk));
llvm_unreachable("Unimplemented!");
// Everything else is legal.
return Op;
}
static bool areOnlyUsersOf(SDNode *N, ArrayRef<SDValue> ValidUsers) {