From 1efba0ecb4d0b3807c48e6e0f74e3ce5c9fad809 Mon Sep 17 00:00:00 2001
From: Evan Cheng <evan.cheng@apple.com>
Date: Tue, 29 Aug 2006 06:42:35 +0000
Subject: [PATCH] Move isCommutativeBinOp from SelectionDAG.cpp and
 DAGCombiner.cpp out. Make it a static method of SelectionDAG.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29951 91177308-0d34-0410-b5e6-96231b3b80d8
---
 include/llvm/CodeGen/SelectionDAG.h       | 19 +++++++++++++++++++
 lib/CodeGen/SelectionDAG/DAGCombiner.cpp  | 19 +++----------------
 lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 15 ---------------
 3 files changed, 22 insertions(+), 31 deletions(-)

diff --git a/include/llvm/CodeGen/SelectionDAG.h b/include/llvm/CodeGen/SelectionDAG.h
index 3b6d1a15ab6..deae2e3f23f 100644
--- a/include/llvm/CodeGen/SelectionDAG.h
+++ b/include/llvm/CodeGen/SelectionDAG.h
@@ -388,6 +388,25 @@ public:
   /// of the SDNodes* in assigned order by reference.
   unsigned AssignTopologicalOrder(std::vector<SDNode*> &TopOrder);
 
+  /// isCommutativeBinOp - Returns true if the opcode is a commutative binary
+  /// operation.
+  static bool isCommutativeBinOp(unsigned Opcode) {
+    switch (Opcode) {
+    case ISD::ADD:
+    case ISD::MUL:
+    case ISD::MULHU:
+    case ISD::MULHS:
+    case ISD::FADD:
+    case ISD::FMUL:
+    case ISD::AND:
+    case ISD::OR:
+    case ISD::XOR:
+    case ISD::ADDC: 
+    case ISD::ADDE: return true;
+    default: return false;
+    }
+  }
+
   void dump() const;
 
 private:
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 620feb9aa3d..afe1fe57cd0 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -306,19 +306,6 @@ static bool isOneUseSetCC(SDOperand N) {
   return false;
 }
 
-// FIXME: This should probably go in the ISD class rather than being duplicated
-// in several files.
-static bool isCommutativeBinOp(unsigned Opcode) {
-  switch (Opcode) {
-    case ISD::ADD:
-    case ISD::MUL:
-    case ISD::AND:
-    case ISD::OR:
-    case ISD::XOR: return true;
-    default: return false; // FIXME: Need commutative info for user ops!
-  }
-}
-
 SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
   MVT::ValueType VT = N0.getValueType();
   // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
@@ -3456,7 +3443,7 @@ SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
           return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
         if (N0.getOperand(1) == N1.getOperand(1))
           return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond);
-        if (isCommutativeBinOp(N0.getOpcode())) {
+        if (DAG.isCommutativeBinOp(N0.getOpcode())) {
           // If X op Y == Y op X, try other combinations.
           if (N0.getOperand(0) == N1.getOperand(1))
             return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
@@ -3499,7 +3486,7 @@ SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
         return DAG.getSetCC(VT, N0.getOperand(1),
                         DAG.getConstant(0, N0.getValueType()), Cond);
       if (N0.getOperand(1) == N1) {
-        if (isCommutativeBinOp(N0.getOpcode()))
+        if (DAG.isCommutativeBinOp(N0.getOpcode()))
           return DAG.getSetCC(VT, N0.getOperand(0),
                           DAG.getConstant(0, N0.getValueType()), Cond);
         else {
@@ -3521,7 +3508,7 @@ SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
         return DAG.getSetCC(VT, N1.getOperand(1),
                         DAG.getConstant(0, N1.getValueType()), Cond);
       } else if (N1.getOperand(1) == N0) {
-        if (isCommutativeBinOp(N1.getOpcode())) {
+        if (DAG.isCommutativeBinOp(N1.getOpcode())) {
           return DAG.getSetCC(VT, N1.getOperand(0),
                           DAG.getConstant(0, N1.getValueType()), Cond);
         } else {
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index cb9ad98550b..4fa168fccde 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -38,21 +38,6 @@ static SDVTList makeVTList(const MVT::ValueType *VTs, unsigned NumVTs) {
   return Res;
 }
 
-static bool isCommutativeBinOp(unsigned Opcode) {
-  switch (Opcode) {
-  case ISD::ADD:
-  case ISD::MUL:
-  case ISD::MULHU:
-  case ISD::MULHS:
-  case ISD::FADD:
-  case ISD::FMUL:
-  case ISD::AND:
-  case ISD::OR:
-  case ISD::XOR: return true;
-  default: return false; // FIXME: Need commutative info for user ops!
-  }
-}
-
 // isInvertibleForFree - Return true if there is no cost to emitting the logical
 // inverse of this node.
 static bool isInvertibleForFree(SDOperand N) {