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Add extra operand to CALLSEQ_START to keep frame part set up previously
Using arguments with attribute inalloca creates problems for verification of machine representation. This attribute instructs the backend that the argument is prepared in stack prior to CALLSEQ_START..CALLSEQ_END sequence (see http://llvm.org/docs/InAlloca.htm for details). Frame size stored in CALLSEQ_START in this case does not count the size of this argument. However CALLSEQ_END still keeps total frame size, as caller can be responsible for cleanup of entire frame. So CALLSEQ_START and CALLSEQ_END keep different frame size and the difference is treated by MachineVerifier as stack error. Currently there is no way to distinguish this case from actual errors. This patch adds additional argument to CALLSEQ_START and its target-specific counterparts to keep size of stack that is set up prior to the call frame sequence. This argument allows MachineVerifier to calculate actual frame size associated with frame setup instruction and correctly process the case of inalloca arguments. The changes made by the patch are: - Frame setup instructions get the second mandatory argument. It affects all targets that use frame pseudo instructions and touched many files although the changes are uniform. - Access to frame properties are implemented using special instructions rather than calls getOperand(N).getImm(). For X86 and ARM such replacement was made previously. - Changes that reflect appearance of additional argument of frame setup instruction. These involve proper instruction initialization and methods that access instruction arguments. - MachineVerifier retrieves frame size using method, which reports sum of frame parts initialized inside frame instruction pair and outside it. The patch implements approach proposed by Quentin Colombet in https://bugs.llvm.org/show_bug.cgi?id=27481#c1. It fixes 9 tests failed with machine verifier enabled and listed in PR27481. Differential Revision: https://reviews.llvm.org/D32394 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302527 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Serge Pavlov
parent
5cd1e6d400
commit
1f4a80fdc1
@ -644,6 +644,13 @@ namespace ISD {
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/// of a call sequence, and carry arbitrary information that target might
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/// want to know. The first operand is a chain, the rest are specified by
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/// the target and not touched by the DAG optimizers.
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/// Targets that may use stack to pass call arguments define additional
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/// operands:
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/// - size of the call frame part that must be set up within the
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/// CALLSEQ_START..CALLSEQ_END pair,
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/// - part of the call frame prepared prior to CALLSEQ_START.
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/// Both these parameters must be constants, their sum is the total call
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/// frame size.
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/// CALLSEQ_START..CALLSEQ_END pairs may not be nested.
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CALLSEQ_START, // Beginning of a call sequence
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CALLSEQ_END, // End of a call sequence
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@ -737,11 +737,15 @@ public:
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/// \brief Create a logical NOT operation as (XOR Val, BooleanOne).
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SDValue getLogicalNOT(const SDLoc &DL, SDValue Val, EVT VT);
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/// Return a new CALLSEQ_START node, which always must have a glue result
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/// (to ensure it's not CSE'd). CALLSEQ_START does not have a useful SDLoc.
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SDValue getCALLSEQ_START(SDValue Chain, SDValue Op, const SDLoc &DL) {
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/// Return a new CALLSEQ_START node, that starts new call frame, in which
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/// InSize bytes are set up inside CALLSEQ_START..CALLSEQ_END sequence and
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/// OutSize specifies part of the frame set up prior to the sequence.
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SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize,
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const SDLoc &DL) {
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SDVTList VTs = getVTList(MVT::Other, MVT::Glue);
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SDValue Ops[] = { Chain, Op };
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SDValue Ops[] = { Chain,
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getIntPtrConstant(InSize, DL, true),
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getIntPtrConstant(OutSize, DL, true) };
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return getNode(ISD::CALLSEQ_START, DL, VTs, Ops);
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}
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@ -172,11 +172,22 @@ public:
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/// inalloca arguments. This function reports only the size of the frame part
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/// that is set up between the frame setup and destroy pseudo instructions.
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int64_t getFrameSize(const MachineInstr &I) const {
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assert(isFrameInstr(I));
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assert(isFrameInstr(I) && "Not a frame instruction");
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assert(I.getOperand(0).getImm() >= 0);
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return I.getOperand(0).getImm();
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}
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/// Returns the total frame size, which is made up of the space set up inside
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/// the pair of frame start-stop instructions and the space that is set up
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/// prior to the pair.
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int64_t getFrameTotalSize(const MachineInstr &I) const {
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if (isFrameSetup(I)) {
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assert(I.getOperand(1).getImm() >= 0 && "Frame size must not be negative");
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return getFrameSize(I) + I.getOperand(1).getImm();
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}
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return getFrameSize(I);
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}
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unsigned getCatchReturnOpcode() const { return CatchRetOpcode; }
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unsigned getReturnOpcode() const { return ReturnOpcode; }
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@ -281,7 +281,7 @@ def SDTConvertOp : SDTypeProfile<1, 5, [ //cvtss, su, us, uu, ff, fs, fu, sf, su
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]>;
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class SDCallSeqStart<list<SDTypeConstraint> constraints> :
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SDTypeProfile<0, 1, constraints>;
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SDTypeProfile<0, 2, constraints>;
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class SDCallSeqEnd<list<SDTypeConstraint> constraints> :
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SDTypeProfile<0, 2, constraints>;
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@ -2063,12 +2063,12 @@ void MachineVerifier::verifyStackFrame() {
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if (I.getOpcode() == FrameSetupOpcode) {
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if (BBState.ExitIsSetup)
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report("FrameSetup is after another FrameSetup", &I);
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BBState.ExitValue -= TII->getFrameSize(I);
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BBState.ExitValue -= TII->getFrameTotalSize(I);
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BBState.ExitIsSetup = true;
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}
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if (I.getOpcode() == FrameDestroyOpcode) {
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int Size = TII->getFrameSize(I);
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int Size = TII->getFrameTotalSize(I);
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if (!BBState.ExitIsSetup)
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report("FrameDestroy is not after a FrameSetup", &I);
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int AbsSPAdj = BBState.ExitValue < 0 ? -BBState.ExitValue :
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@ -622,7 +622,7 @@ bool FastISel::selectStackmap(const CallInst *I) {
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// have to worry about calling conventions and target-specific lowering code.
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// Instead we perform the call lowering right here.
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//
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// CALLSEQ_START(0...)
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// CALLSEQ_START(0, 0...)
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// STACKMAP(id, nbytes, ...)
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// CALLSEQ_END(0, 0)
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//
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@ -1493,7 +1493,7 @@ void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
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// Chain the dynamic stack allocation so that it doesn't modify the stack
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// pointer when other instructions are using the stack.
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Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true), dl);
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Chain = DAG.getCALLSEQ_START(Chain, 0, 0, dl);
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SDValue Size = Tmp2.getOperand(1);
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SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
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@ -7440,11 +7440,11 @@ void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
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// have to worry about calling conventions and target specific lowering code.
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// Instead we perform the call lowering right here.
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//
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// chain, flag = CALLSEQ_START(chain, 0)
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// chain, flag = CALLSEQ_START(chain, 0, 0)
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// chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
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// chain, flag = CALLSEQ_END(chain, 0, 0, flag)
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//
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Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
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Chain = DAG.getCALLSEQ_START(getRoot(), 0, 0, DL);
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InFlag = Chain.getValue(1);
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// Add the <id> and <numBytes> constants.
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@ -380,7 +380,7 @@ bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
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MIRBuilder.buildSequence(OrigRet.Reg, SplitRegs, RegOffsets);
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}
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CallSeqStart.addImm(Handler.StackSize);
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CallSeqStart.addImm(Handler.StackSize).addImm(0);
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MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP)
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.addImm(Handler.StackSize)
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.addImm(0);
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@ -3014,7 +3014,7 @@ bool AArch64FastISel::processCallArgs(CallLoweringInfo &CLI,
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// Issue CALLSEQ_START
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unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackDown))
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.addImm(NumBytes);
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.addImm(NumBytes).addImm(0);
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// Process the args.
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for (CCValAssign &VA : ArgLocs) {
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@ -3249,9 +3249,7 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
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// Adjust the stack pointer for the new arguments...
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// These operations are automatically eliminated by the prolog/epilog pass
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if (!IsSibCall)
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Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, DL,
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true),
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DL);
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Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL);
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SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, AArch64::SP,
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getPointerTy(DAG.getDataLayout()));
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@ -156,7 +156,8 @@ def AArch64adrp : SDNode<"AArch64ISD::ADRP", SDTIntUnaryOp, []>;
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def AArch64addlow : SDNode<"AArch64ISD::ADDlow", SDTIntBinOp, []>;
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def AArch64LOADgot : SDNode<"AArch64ISD::LOADgot", SDTIntUnaryOp>;
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def AArch64callseq_start : SDNode<"ISD::CALLSEQ_START",
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SDCallSeqStart<[ SDTCisVT<0, i32> ]>,
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SDCallSeqStart<[ SDTCisVT<0, i32>,
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SDTCisVT<1, i32> ]>,
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[SDNPHasChain, SDNPOutGlue]>;
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def AArch64callseq_end : SDNode<"ISD::CALLSEQ_END",
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SDCallSeqEnd<[ SDTCisVT<0, i32>,
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@ -328,8 +329,9 @@ include "AArch64InstrFormats.td"
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let Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1 in {
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// We set Sched to empty list because we expect these instructions to simply get
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// removed in most cases.
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def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
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[(AArch64callseq_start timm:$amt)]>, Sched<[]>;
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def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
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[(AArch64callseq_start timm:$amt1, timm:$amt2)]>,
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Sched<[]>;
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def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
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[(AArch64callseq_end timm:$amt1, timm:$amt2)]>,
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Sched<[]>;
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@ -404,21 +404,11 @@ public:
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/// Returns predicate register associated with the given frame instruction.
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unsigned getFramePred(const MachineInstr &MI) const {
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assert(isFrameInstr(MI));
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if (isFrameSetup(MI))
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// Operands of ADJCALLSTACKDOWN:
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// - argument declared in ADJCALLSTACKDOWN pattern:
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// 0 - frame size
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// 1 - predicate code (like ARMCC::AL)
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// - added by predOps:
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// 2 - predicate reg
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return MI.getOperand(2).getReg();
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assert(MI.getOpcode() == ARM::ADJCALLSTACKUP ||
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MI.getOpcode() == ARM::tADJCALLSTACKUP);
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// Operands of ADJCALLSTACKUP:
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// - argument declared in ADJCALLSTACKUP pattern:
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// Operands of ADJCALLSTACKDOWN/ADJCALLSTACKUP:
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// - argument declared in the pattern:
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// 0 - frame size
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// 1 - arg of CALLSEQ_END
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// 2 - predicate code
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// 1 - arg of CALLSEQ_START/CALLSEQ_END
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// 2 - predicate code (like ARMCC::AL)
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// - added by predOps:
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// 3 - predicate reg
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return MI.getOperand(3).getReg();
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@ -433,7 +433,7 @@ bool ARMCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
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// We now know the size of the stack - update the ADJCALLSTACKDOWN
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// accordingly.
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CallSeqStart.addImm(ArgHandler.StackSize).add(predOps(ARMCC::AL));
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CallSeqStart.addImm(ArgHandler.StackSize).addImm(0).add(predOps(ARMCC::AL));
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MIRBuilder.buildInstr(ARM::ADJCALLSTACKUP)
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.addImm(ArgHandler.StackSize)
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@ -1949,7 +1949,7 @@ bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
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unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(AdjStackDown))
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.addImm(NumBytes));
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.addImm(NumBytes).addImm(0));
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// Process the args.
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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@ -1817,8 +1817,7 @@ ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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// Adjust the stack pointer for the new arguments...
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// These operations are automatically eliminated by the prolog/epilog pass
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if (!isSibCall)
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Chain = DAG.getCALLSEQ_START(Chain,
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DAG.getIntPtrConstant(NumBytes, dl, true), dl);
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Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
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SDValue StackPtr =
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DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy(DAG.getDataLayout()));
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@ -16,7 +16,8 @@
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//
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// Type profiles.
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def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
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def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>,
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SDTCisVT<1, i32> ]>;
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def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
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def SDT_ARMStructByVal : SDTypeProfile<0, 4,
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[SDTCisVT<0, i32>, SDTCisVT<1, i32>,
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@ -1968,8 +1969,8 @@ PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
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[(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
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def ADJCALLSTACKDOWN :
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PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
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[(ARMcallseq_start timm:$amt)]>;
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PseudoInst<(outs), (ins i32imm:$amt, i32imm:$amt2, pred:$p), NoItinerary,
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[(ARMcallseq_start timm:$amt, timm:$amt2)]>;
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}
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def HINT : AI<(outs), (ins imm0_239:$imm), MiscFrm, NoItinerary,
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@ -284,8 +284,8 @@ def tADJCALLSTACKUP :
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Requires<[IsThumb, IsThumb1Only]>;
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def tADJCALLSTACKDOWN :
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PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
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[(ARMcallseq_start imm:$amt)]>,
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PseudoInst<(outs), (ins i32imm:$amt, i32imm:$amt2), NoItinerary,
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[(ARMcallseq_start imm:$amt, imm:$amt2)]>,
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Requires<[IsThumb, IsThumb1Only]>;
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}
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@ -375,7 +375,7 @@ MachineBasicBlock::iterator AVRFrameLowering::eliminateCallFramePseudoInstr(
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DebugLoc DL = MI->getDebugLoc();
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unsigned int Opcode = MI->getOpcode();
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int Amount = MI->getOperand(0).getImm();
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int Amount = TII.getFrameSize(*MI);
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// Adjcallstackup does not need to allocate stack space for the call, instead
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// we insert push instructions that will allocate the necessary stack.
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@ -1166,8 +1166,7 @@ SDValue AVRTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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// Get a count of how many bytes are to be pushed on the stack.
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unsigned NumBytes = CCInfo.getNextStackOffset();
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Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, DL, true),
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DL);
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Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL);
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SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
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@ -17,7 +17,7 @@ include "AVRInstrFormats.td"
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// AVR Type Profiles
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//===----------------------------------------------------------------------===//
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def SDT_AVRCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i16>]>;
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def SDT_AVRCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>;
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def SDT_AVRCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>;
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def SDT_AVRCall : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
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def SDT_AVRWrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
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@ -333,9 +333,9 @@ let Defs = [SP, SREG],
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Uses = [SP] in
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{
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def ADJCALLSTACKDOWN : Pseudo<(outs),
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(ins i16imm:$amt),
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(ins i16imm:$amt, i16imm:$amt2),
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"#ADJCALLSTACKDOWN",
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[(AVRcallseq_start timm:$amt)]>;
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[(AVRcallseq_start timm:$amt, timm:$amt2)]>;
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// R31R30 is used to update SP, since it is a scratch reg and this instruction
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// is placed after the function call then R31R30 should be always free.
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@ -257,8 +257,7 @@ SDValue BPFTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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}
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auto PtrVT = getPointerTy(MF.getDataLayout());
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Chain = DAG.getCALLSEQ_START(
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Chain, DAG.getConstant(NumBytes, CLI.DL, PtrVT, true), CLI.DL);
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Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, CLI.DL);
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SmallVector<std::pair<unsigned, SDValue>, MaxArgs> RegsToPass;
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@ -16,7 +16,8 @@ include "BPFInstrFormats.td"
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// Instruction Operands and Patterns
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// These are target-independent nodes, but have target-specific formats.
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def SDT_BPFCallSeqStart : SDCallSeqStart<[SDTCisVT<0, iPTR>]>;
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def SDT_BPFCallSeqStart : SDCallSeqStart<[SDTCisVT<0, iPTR>,
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SDTCisVT<1, iPTR>]>;
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def SDT_BPFCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
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def SDT_BPFCall : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
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def SDT_BPFSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>;
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@ -445,9 +446,9 @@ let isReturn = 1, isTerminator = 1, hasDelaySlot=0, isBarrier = 1,
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// ADJCALLSTACKDOWN/UP pseudo insns
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let Defs = [R11], Uses = [R11] in {
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def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
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"#ADJCALLSTACKDOWN $amt",
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[(BPFcallseq_start timm:$amt)]>;
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def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
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"#ADJCALLSTACKDOWN $amt1 $amt2",
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[(BPFcallseq_start timm:$amt1, timm:$amt2)]>;
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def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
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"#ADJCALLSTACKUP $amt1 $amt2",
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[(BPFcallseq_end timm:$amt1, timm:$amt2)]>;
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@ -848,8 +848,7 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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SDValue Glue;
|
||||
if (!IsTailCall) {
|
||||
SDValue C = DAG.getConstant(NumBytes, dl, PtrVT, true);
|
||||
Chain = DAG.getCALLSEQ_START(Chain, C, dl);
|
||||
Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
|
||||
Glue = Chain.getValue(1);
|
||||
}
|
||||
|
||||
|
||||
@ -714,7 +714,8 @@ def: Pat<(i1 0), (PS_false)>;
|
||||
def: Pat<(i1 1), (PS_true)>;
|
||||
|
||||
// Pseudo instructions.
|
||||
def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
|
||||
def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>,
|
||||
SDTCisVT<1, i32> ]>;
|
||||
def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
|
||||
SDTCisVT<1, i32> ]>;
|
||||
|
||||
@ -732,8 +733,8 @@ def HexagonTCRet : SDNode<"HexagonISD::TC_RETURN", SDT_SPCall,
|
||||
[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
|
||||
|
||||
|
||||
def: Pat<(callseq_start timm:$amt),
|
||||
(ADJCALLSTACKDOWN imm:$amt)>;
|
||||
def: Pat<(callseq_start timm:$amt, timm:$amt2),
|
||||
(ADJCALLSTACKDOWN imm:$amt, imm:$amt2)>;
|
||||
def: Pat<(callseq_end timm:$amt1, timm:$amt2),
|
||||
(ADJCALLSTACKUP imm:$amt1, imm:$amt2)>;
|
||||
|
||||
|
||||
@ -80,7 +80,7 @@ def PS_false : InstHexagon<(outs PredRegs:$dst), (ins), "",
|
||||
[(set I1:$dst, 0)], "", C2_andn.Itinerary, TypeCR>;
|
||||
|
||||
let Defs = [R29, R30], Uses = [R31, R30, R29], isPseudo = 1 in
|
||||
def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
|
||||
def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
|
||||
".error \"should not emit\" ", []>;
|
||||
|
||||
let Defs = [R29, R30, R31], Uses = [R29], isPseudo = 1 in
|
||||
|
||||
@ -649,10 +649,7 @@ SDValue LanaiTargetLowering::LowerCCCCallTo(
|
||||
ByValArgs.push_back(FIPtr);
|
||||
}
|
||||
|
||||
Chain = DAG.getCALLSEQ_START(
|
||||
Chain,
|
||||
DAG.getConstant(NumBytes, DL, getPointerTy(DAG.getDataLayout()), true),
|
||||
DL);
|
||||
Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL);
|
||||
|
||||
SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
|
||||
SmallVector<SDValue, 12> MemOpChains;
|
||||
|
||||
@ -22,7 +22,8 @@ include "LanaiInstrFormats.td"
|
||||
// -------------------------------------------------- //
|
||||
|
||||
// These are target-independent nodes, but have target-specific formats.
|
||||
def SDT_LanaiCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
|
||||
def SDT_LanaiCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>,
|
||||
SDTCisVT<1, i32>]>;
|
||||
def SDT_LanaiCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
|
||||
SDTCisVT<1, i32>]>;
|
||||
def SDT_LanaiCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>;
|
||||
@ -750,9 +751,9 @@ let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1,
|
||||
// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
|
||||
// sub / add which can clobber SP.
|
||||
let Defs = [SP], Uses = [SP] in {
|
||||
def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
|
||||
"#ADJCALLSTACKDOWN $amt",
|
||||
[(CallSeqStart timm:$amt)]>;
|
||||
def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
|
||||
"#ADJCALLSTACKDOWN $amt1 $amt2",
|
||||
[(CallSeqStart timm:$amt1, timm:$amt2)]>;
|
||||
def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
|
||||
"#ADJCALLSTACKUP $amt1 $amt2",
|
||||
[(CallSeqEnd timm:$amt1, timm:$amt2)]>;
|
||||
|
||||
@ -236,7 +236,7 @@ MachineBasicBlock::iterator MSP430FrameLowering::eliminateCallFramePseudoInstr(
|
||||
// adjcallstackdown instruction into 'add SP, <amt>'
|
||||
// TODO: consider using push / pop instead of sub + store / add
|
||||
MachineInstr &Old = *I;
|
||||
uint64_t Amount = Old.getOperand(0).getImm();
|
||||
uint64_t Amount = TII.getFrameSize(Old);
|
||||
if (Amount != 0) {
|
||||
// We need to keep the stack aligned properly. To do this, we round the
|
||||
// amount of space needed for the outgoing arguments up to the next
|
||||
@ -252,8 +252,7 @@ MachineBasicBlock::iterator MSP430FrameLowering::eliminateCallFramePseudoInstr(
|
||||
} else {
|
||||
assert(Old.getOpcode() == TII.getCallFrameDestroyOpcode());
|
||||
// factor out the amount the callee already popped.
|
||||
uint64_t CalleeAmt = Old.getOperand(1).getImm();
|
||||
Amount -= CalleeAmt;
|
||||
Amount -= TII.getFramePoppedByCallee(Old);
|
||||
if (Amount)
|
||||
New = BuildMI(MF, Old.getDebugLoc(), TII.get(MSP430::ADD16ri),
|
||||
MSP430::SP)
|
||||
@ -272,7 +271,7 @@ MachineBasicBlock::iterator MSP430FrameLowering::eliminateCallFramePseudoInstr(
|
||||
} else if (I->getOpcode() == TII.getCallFrameDestroyOpcode()) {
|
||||
// If we are performing frame pointer elimination and if the callee pops
|
||||
// something off the stack pointer, add it back.
|
||||
if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
|
||||
if (uint64_t CalleeAmt = TII.getFramePoppedByCallee(*I)) {
|
||||
MachineInstr &Old = *I;
|
||||
MachineInstr *New =
|
||||
BuildMI(MF, Old.getDebugLoc(), TII.get(MSP430::SUB16ri), MSP430::SP)
|
||||
|
||||
@ -615,8 +615,7 @@ SDValue MSP430TargetLowering::LowerCCCCallTo(
|
||||
unsigned NumBytes = CCInfo.getNextStackOffset();
|
||||
auto PtrVT = getPointerTy(DAG.getDataLayout());
|
||||
|
||||
Chain = DAG.getCALLSEQ_START(Chain,
|
||||
DAG.getConstant(NumBytes, dl, PtrVT, true), dl);
|
||||
Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
|
||||
|
||||
SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
|
||||
SmallVector<SDValue, 12> MemOpChains;
|
||||
|
||||
@ -85,6 +85,12 @@ public:
|
||||
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
|
||||
const DebugLoc &DL,
|
||||
int *BytesAdded = nullptr) const override;
|
||||
|
||||
int64_t getFramePoppedByCallee(const MachineInstr &I) const {
|
||||
assert(isFrameInstr(I) && "Not a frame instruction");
|
||||
assert(I.getOperand(1).getImm() >= 0 && "Size must not be negative");
|
||||
return I.getOperand(1).getImm();
|
||||
}
|
||||
};
|
||||
|
||||
}
|
||||
|
||||
@ -23,7 +23,8 @@ class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>;
|
||||
// Type Profiles.
|
||||
//===----------------------------------------------------------------------===//
|
||||
def SDT_MSP430Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
|
||||
def SDT_MSP430CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i16>]>;
|
||||
def SDT_MSP430CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i16>,
|
||||
SDTCisVT<1, i16>]>;
|
||||
def SDT_MSP430CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>;
|
||||
def SDT_MSP430Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>,
|
||||
SDTCisPtrTy<0>]>;
|
||||
@ -113,9 +114,9 @@ def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
|
||||
// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
|
||||
// sub / add which can clobber SR.
|
||||
let Defs = [SP, SR], Uses = [SP] in {
|
||||
def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i16imm:$amt),
|
||||
def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i16imm:$amt1, i16imm:$amt2),
|
||||
"#ADJCALLSTACKDOWN",
|
||||
[(MSP430callseq_start timm:$amt)]>;
|
||||
[(MSP430callseq_start timm:$amt1, timm:$amt2)]>;
|
||||
def ADJCALLSTACKUP : Pseudo<(outs), (ins i16imm:$amt1, i16imm:$amt2),
|
||||
"#ADJCALLSTACKUP",
|
||||
[(MSP430callseq_end timm:$amt1, timm:$amt2)]>;
|
||||
|
||||
@ -1133,7 +1133,7 @@ bool MipsFastISel::processCallArgs(CallLoweringInfo &CLI,
|
||||
if (NumBytes < 16)
|
||||
NumBytes = 16;
|
||||
|
||||
emitInst(Mips::ADJCALLSTACKDOWN).addImm(16);
|
||||
emitInst(Mips::ADJCALLSTACKDOWN).addImm(16).addImm(0);
|
||||
// Process the args.
|
||||
MVT firstMVT;
|
||||
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
||||
|
||||
@ -2787,7 +2787,7 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
||||
SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true);
|
||||
|
||||
if (!IsTailCall)
|
||||
Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal, DL);
|
||||
Chain = DAG.getCALLSEQ_START(Chain, NextStackOffset, 0, DL);
|
||||
|
||||
SDValue StackPtr =
|
||||
DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP,
|
||||
|
||||
@ -21,7 +21,7 @@ def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
|
||||
SDTCisSameAs<1, 2>,
|
||||
SDTCisSameAs<3, 4>,
|
||||
SDTCisInt<4>]>;
|
||||
def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
|
||||
def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
|
||||
def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
|
||||
def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
|
||||
def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
|
||||
@ -1719,8 +1719,8 @@ let isReturn=1, isTerminator=1, isBarrier=1, hasCtrlDep=1, isCTI=1 in {
|
||||
}
|
||||
|
||||
let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
|
||||
def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
|
||||
[(callseq_start timm:$amt)]>;
|
||||
def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
|
||||
[(callseq_start timm:$amt1, timm:$amt2)]>;
|
||||
def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
|
||||
[(callseq_end timm:$amt1, timm:$amt2)]>;
|
||||
}
|
||||
|
||||
@ -1430,8 +1430,7 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
||||
return Chain;
|
||||
|
||||
SDValue tempChain = Chain;
|
||||
Chain = DAG.getCALLSEQ_START(
|
||||
Chain, DAG.getIntPtrConstant(uniqueCallSite, dl, true), dl);
|
||||
Chain = DAG.getCALLSEQ_START(Chain, uniqueCallSite, 0, dl);
|
||||
SDValue InFlag = Chain.getValue(1);
|
||||
|
||||
unsigned paramCount = 0;
|
||||
|
||||
@ -3101,7 +3101,8 @@ def : Pat<(brcond (i1 (setne Int1Regs:$a, -1)), bb:$target),
|
||||
(CBranchOther Int1Regs:$a, bb:$target)>;
|
||||
|
||||
// Call
|
||||
def SDT_NVPTXCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
|
||||
def SDT_NVPTXCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>,
|
||||
SDTCisVT<1, i32>]>;
|
||||
def SDT_NVPTXCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
|
||||
|
||||
def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_NVPTXCallSeqStart,
|
||||
@ -3126,10 +3127,10 @@ class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
|
||||
: NVPTXInst<outs, ins, asmstr, pattern>;
|
||||
|
||||
def Callseq_Start :
|
||||
NVPTXInst<(outs), (ins i32imm:$amt),
|
||||
"\\{ // callseq $amt\n"
|
||||
NVPTXInst<(outs), (ins i32imm:$amt1, i32imm:$amt2),
|
||||
"\\{ // callseq $amt1, $amt2\n"
|
||||
"\t.reg .b32 temp_param_reg;",
|
||||
[(callseq_start timm:$amt)]>;
|
||||
[(callseq_start timm:$amt1, timm:$amt2)]>;
|
||||
def Callseq_End :
|
||||
NVPTXInst<(outs), (ins i32imm:$amt1, i32imm:$amt2),
|
||||
"\\} // callseq $amt1",
|
||||
|
||||
@ -1330,7 +1330,7 @@ bool PPCFastISel::processCallArgs(SmallVectorImpl<Value*> &Args,
|
||||
// Issue CALLSEQ_START.
|
||||
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
||||
TII.get(TII.getCallFrameSetupOpcode()))
|
||||
.addImm(NumBytes);
|
||||
.addImm(NumBytes).addImm(0);
|
||||
|
||||
// Prepare to assign register arguments. Every argument uses up a
|
||||
// GPR protocol register even if it's passed in a floating-point
|
||||
|
||||
@ -4949,8 +4949,7 @@ SDValue PPCTargetLowering::LowerCall_32SVR4(
|
||||
|
||||
// Adjust the stack pointer for the new arguments...
|
||||
// These operations are automatically eliminated by the prolog/epilog pass
|
||||
Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
|
||||
dl);
|
||||
Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
|
||||
SDValue CallSeqStart = Chain;
|
||||
|
||||
// Load the return address and frame pointer so it can be moved somewhere else
|
||||
@ -5000,9 +4999,8 @@ SDValue PPCTargetLowering::LowerCall_32SVR4(
|
||||
Flags, DAG, dl);
|
||||
|
||||
// This must go outside the CALLSEQ_START..END.
|
||||
SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
|
||||
CallSeqStart.getNode()->getOperand(1),
|
||||
SDLoc(MemcpyCall));
|
||||
SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, NumBytes, 0,
|
||||
SDLoc(MemcpyCall));
|
||||
DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
|
||||
NewCallSeqStart.getNode());
|
||||
Chain = CallSeqStart = NewCallSeqStart;
|
||||
@ -5083,9 +5081,9 @@ SDValue PPCTargetLowering::createMemcpyOutsideCallSeq(
|
||||
CallSeqStart.getNode()->getOperand(0),
|
||||
Flags, DAG, dl);
|
||||
// The MEMCPY must go outside the CALLSEQ_START..END.
|
||||
SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
|
||||
CallSeqStart.getNode()->getOperand(1),
|
||||
SDLoc(MemcpyCall));
|
||||
int64_t FrameSize = CallSeqStart.getConstantOperandVal(1);
|
||||
SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, FrameSize, 0,
|
||||
SDLoc(MemcpyCall));
|
||||
DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
|
||||
NewCallSeqStart.getNode());
|
||||
return NewCallSeqStart;
|
||||
@ -5268,8 +5266,7 @@ SDValue PPCTargetLowering::LowerCall_64SVR4(
|
||||
// Adjust the stack pointer for the new arguments...
|
||||
// These operations are automatically eliminated by the prolog/epilog pass
|
||||
if (!IsSibCall)
|
||||
Chain = DAG.getCALLSEQ_START(Chain,
|
||||
DAG.getIntPtrConstant(NumBytes, dl, true), dl);
|
||||
Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
|
||||
SDValue CallSeqStart = Chain;
|
||||
|
||||
// Load the return address and frame pointer so it can be move somewhere else
|
||||
@ -5828,8 +5825,7 @@ SDValue PPCTargetLowering::LowerCall_Darwin(
|
||||
|
||||
// Adjust the stack pointer for the new arguments...
|
||||
// These operations are automatically eliminated by the prolog/epilog pass
|
||||
Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
|
||||
dl);
|
||||
Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
|
||||
SDValue CallSeqStart = Chain;
|
||||
|
||||
// Load the return address and frame pointer so it can be move somewhere else
|
||||
|
||||
@ -33,7 +33,8 @@ def SDT_PPCVexts : SDTypeProfile<1, 2, [
|
||||
SDTCisVT<0, f64>, SDTCisVT<1, f64>, SDTCisPtrTy<2>
|
||||
]>;
|
||||
|
||||
def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
|
||||
def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>,
|
||||
SDTCisVT<1, i32> ]>;
|
||||
def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
|
||||
SDTCisVT<1, i32> ]>;
|
||||
def SDT_PPCvperm : SDTypeProfile<1, 3, [
|
||||
@ -1099,9 +1100,11 @@ multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
|
||||
|
||||
let hasCtrlDep = 1 in {
|
||||
let Defs = [R1], Uses = [R1] in {
|
||||
def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
|
||||
[(callseq_start timm:$amt)]>;
|
||||
def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt2",
|
||||
def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2),
|
||||
"#ADJCALLSTACKDOWN $amt1 $amt2",
|
||||
[(callseq_start timm:$amt1, timm:$amt2)]>;
|
||||
def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2),
|
||||
"#ADJCALLSTACKUP $amt1 $amt2",
|
||||
[(callseq_end timm:$amt1, timm:$amt2)]>;
|
||||
}
|
||||
|
||||
|
||||
@ -99,7 +99,8 @@ protected:
|
||||
// Don't really need to save data to the stack - the clobbered
|
||||
// registers are already saved when the SDNode (e.g. PPCaddiTlsgdLAddr)
|
||||
// gets translated to the pseudo instruction (e.g. ADDItlsgdLADDR).
|
||||
BuildMI(MBB, I, DL, TII->get(PPC::ADJCALLSTACKDOWN)).addImm(0);
|
||||
BuildMI(MBB, I, DL, TII->get(PPC::ADJCALLSTACKDOWN)).addImm(0)
|
||||
.addImm(0);
|
||||
|
||||
// Expand into two ops built prior to the existing instruction.
|
||||
MachineInstr *Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3)
|
||||
|
||||
@ -773,8 +773,7 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
|
||||
}
|
||||
}
|
||||
|
||||
Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, dl, true),
|
||||
dl);
|
||||
Chain = DAG.getCALLSEQ_START(Chain, ArgsSize, 0, dl);
|
||||
|
||||
SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
|
||||
SmallVector<SDValue, 8> MemOpChains;
|
||||
@ -1165,8 +1164,7 @@ SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
|
||||
// Adjust the stack pointer to make room for the arguments.
|
||||
// FIXME: Use hasReservedCallFrame to avoid %sp adjustments around all calls
|
||||
// with more than 6 arguments.
|
||||
Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, DL, true),
|
||||
DL);
|
||||
Chain = DAG.getCALLSEQ_START(Chain, ArgsSize, 0, DL);
|
||||
|
||||
// Collect the set of registers to pass to the function and their values.
|
||||
// This will be emitted as a sequence of CopyToReg nodes glued to the call
|
||||
@ -2058,7 +2056,7 @@ SDValue SparcTargetLowering::LowerGlobalTLSAddress(SDValue Op,
|
||||
SDValue Chain = DAG.getEntryNode();
|
||||
SDValue InFlag;
|
||||
|
||||
Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(1, DL, true), DL);
|
||||
Chain = DAG.getCALLSEQ_START(Chain, 1, 0, DL);
|
||||
Chain = DAG.getCopyToReg(Chain, DL, SP::O0, Argument, InFlag);
|
||||
InFlag = Chain.getValue(1);
|
||||
SDValue Callee = DAG.getTargetExternalSymbol("__tls_get_addr", PtrVT);
|
||||
|
||||
@ -195,7 +195,8 @@ def SPsjlj_longjmp: SDNode<"SPISD::EH_SJLJ_LONGJMP",
|
||||
[SDNPHasChain, SDNPSideEffect]>;
|
||||
|
||||
// These are target-independent nodes, but have target-specific formats.
|
||||
def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
|
||||
def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>,
|
||||
SDTCisVT<1, i32> ]>;
|
||||
def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
|
||||
SDTCisVT<1, i32> ]>;
|
||||
|
||||
@ -404,9 +405,9 @@ let Defs = [O7] in {
|
||||
}
|
||||
|
||||
let Defs = [O6], Uses = [O6] in {
|
||||
def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
|
||||
"!ADJCALLSTACKDOWN $amt",
|
||||
[(callseq_start timm:$amt)]>;
|
||||
def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
|
||||
"!ADJCALLSTACKDOWN $amt1, $amt2",
|
||||
[(callseq_start timm:$amt1, timm:$amt2)]>;
|
||||
def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
|
||||
"!ADJCALLSTACKUP $amt1",
|
||||
[(callseq_end timm:$amt1, timm:$amt2)]>;
|
||||
|
||||
@ -1110,9 +1110,7 @@ SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI,
|
||||
|
||||
// Mark the start of the call.
|
||||
if (!IsTailCall)
|
||||
Chain = DAG.getCALLSEQ_START(Chain,
|
||||
DAG.getConstant(NumBytes, DL, PtrVT, true),
|
||||
DL);
|
||||
Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL);
|
||||
|
||||
// Copy argument values to their designated locations.
|
||||
SmallVector<std::pair<unsigned, SDValue>, 9> RegsToPass;
|
||||
|
||||
@ -12,8 +12,8 @@
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
let hasNoSchedulingInfo = 1 in {
|
||||
def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
|
||||
[(callseq_start timm:$amt)]>;
|
||||
def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
|
||||
[(callseq_start timm:$amt1, timm:$amt2)]>;
|
||||
def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
|
||||
[(callseq_end timm:$amt1, timm:$amt2)]>;
|
||||
}
|
||||
|
||||
@ -10,7 +10,8 @@
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Type profiles
|
||||
//===----------------------------------------------------------------------===//
|
||||
def SDT_CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i64>]>;
|
||||
def SDT_CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i64>,
|
||||
SDTCisVT<1, i64>]>;
|
||||
def SDT_CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i64>,
|
||||
SDTCisVT<1, i64>]>;
|
||||
def SDT_ZCall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
|
||||
|
||||
@ -19,8 +19,8 @@ let Defs = [ARGUMENTS] in {
|
||||
// Call sequence markers. These have an immediate which represents the amount of
|
||||
// stack space to allocate or free, which is used for varargs lowering.
|
||||
let Uses = [SP32, SP64], Defs = [SP32, SP64], isCodeGenOnly = 1 in {
|
||||
def ADJCALLSTACKDOWN : I<(outs), (ins i32imm:$amt),
|
||||
[(WebAssemblycallseq_start timm:$amt)]>;
|
||||
def ADJCALLSTACKDOWN : I<(outs), (ins i32imm:$amt, i32imm:$amt2),
|
||||
[(WebAssemblycallseq_start timm:$amt, timm:$amt2)]>;
|
||||
def ADJCALLSTACKUP : I<(outs), (ins i32imm:$amt, i32imm:$amt2),
|
||||
[(WebAssemblycallseq_end timm:$amt, timm:$amt2)]>;
|
||||
} // isCodeGenOnly = 1
|
||||
|
||||
@ -25,7 +25,8 @@ def HasSIMD128 : Predicate<"Subtarget->hasSIMD128()">,
|
||||
// WebAssembly-specific DAG Node Types.
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def SDT_WebAssemblyCallSeqStart : SDCallSeqStart<[SDTCisVT<0, iPTR>]>;
|
||||
def SDT_WebAssemblyCallSeqStart : SDCallSeqStart<[SDTCisVT<0, iPTR>,
|
||||
SDTCisVT<1, iPTR>]>;
|
||||
def SDT_WebAssemblyCallSeqEnd :
|
||||
SDCallSeqEnd<[SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>;
|
||||
def SDT_WebAssemblyCall0 : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
|
||||
|
||||
@ -3293,7 +3293,7 @@ bool X86FastISel::fastLowerCall(CallLoweringInfo &CLI) {
|
||||
// Issue CALLSEQ_START
|
||||
unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
|
||||
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackDown))
|
||||
.addImm(NumBytes).addImm(0);
|
||||
.addImm(NumBytes).addImm(0).addImm(0);
|
||||
|
||||
// Walk the register/memloc assignments, inserting copies/loads.
|
||||
const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
|
||||
|
||||
@ -3415,8 +3415,8 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
||||
}
|
||||
|
||||
if (!IsSibcall)
|
||||
Chain = DAG.getCALLSEQ_START(
|
||||
Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
|
||||
Chain = DAG.getCALLSEQ_START(Chain, NumBytesToPush,
|
||||
NumBytes - NumBytesToPush, dl);
|
||||
|
||||
SDValue RetAddrFrIdx;
|
||||
// Load return address for tail calls.
|
||||
@ -14725,7 +14725,7 @@ X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
|
||||
// location.
|
||||
SDValue Chain = DAG.getEntryNode();
|
||||
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
|
||||
Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, DL, true), DL);
|
||||
Chain = DAG.getCALLSEQ_START(Chain, 0, 0, DL);
|
||||
SDValue Args[] = { Chain, Offset };
|
||||
Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
|
||||
Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, DL, true),
|
||||
@ -18572,7 +18572,7 @@ X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
|
||||
|
||||
// Chain the dynamic stack allocation so that it doesn't modify the stack
|
||||
// pointer when other instructions are using the stack.
|
||||
Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true), dl);
|
||||
Chain = DAG.getCALLSEQ_START(Chain, 0, 0, dl);
|
||||
|
||||
bool Is64Bit = Subtarget.is64Bit();
|
||||
MVT SPTy = getPointerTy(DAG.getDataLayout());
|
||||
@ -25787,7 +25787,7 @@ X86TargetLowering::EmitLoweredTLSAddr(MachineInstr &MI,
|
||||
// Emit CALLSEQ_START right before the instruction.
|
||||
unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
|
||||
MachineInstrBuilder CallseqStart =
|
||||
BuildMI(MF, DL, TII.get(AdjStackDown)).addImm(0).addImm(0);
|
||||
BuildMI(MF, DL, TII.get(AdjStackDown)).addImm(0).addImm(0).addImm(0);
|
||||
BB->insert(MachineBasicBlock::iterator(MI), CallseqStart);
|
||||
|
||||
// Emit CALLSEQ_END right after the instruction.
|
||||
|
||||
@ -43,7 +43,8 @@ let hasSideEffects = 0, isNotDuplicable = 1, Uses = [ESP] in
|
||||
// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
|
||||
// sub / add which can clobber EFLAGS.
|
||||
let Defs = [ESP, EFLAGS], Uses = [ESP] in {
|
||||
def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
|
||||
def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs),
|
||||
(ins i32imm:$amt1, i32imm:$amt2, i32imm:$amt3),
|
||||
"#ADJCALLSTACKDOWN",
|
||||
[]>,
|
||||
Requires<[NotLP64]>;
|
||||
@ -52,8 +53,8 @@ def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
|
||||
[(X86callseq_end timm:$amt1, timm:$amt2)]>,
|
||||
Requires<[NotLP64]>;
|
||||
}
|
||||
def : Pat<(X86callseq_start timm:$amt1),
|
||||
(ADJCALLSTACKDOWN32 i32imm:$amt1, 0)>, Requires<[NotLP64]>;
|
||||
def : Pat<(X86callseq_start timm:$amt1, timm:$amt2),
|
||||
(ADJCALLSTACKDOWN32 i32imm:$amt1, i32imm:$amt2, 0)>, Requires<[NotLP64]>;
|
||||
|
||||
|
||||
// ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
|
||||
@ -62,7 +63,8 @@ def : Pat<(X86callseq_start timm:$amt1),
|
||||
// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
|
||||
// sub / add which can clobber EFLAGS.
|
||||
let Defs = [RSP, EFLAGS], Uses = [RSP] in {
|
||||
def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
|
||||
def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs),
|
||||
(ins i32imm:$amt1, i32imm:$amt2, i32imm:$amt3),
|
||||
"#ADJCALLSTACKDOWN",
|
||||
[]>,
|
||||
Requires<[IsLP64]>;
|
||||
@ -71,8 +73,8 @@ def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
|
||||
[(X86callseq_end timm:$amt1, timm:$amt2)]>,
|
||||
Requires<[IsLP64]>;
|
||||
}
|
||||
def : Pat<(X86callseq_start timm:$amt1),
|
||||
(ADJCALLSTACKDOWN64 i32imm:$amt1, 0)>, Requires<[IsLP64]>;
|
||||
def : Pat<(X86callseq_start timm:$amt1, timm:$amt2),
|
||||
(ADJCALLSTACKDOWN64 i32imm:$amt1, i32imm:$amt2, 0)>, Requires<[IsLP64]>;
|
||||
|
||||
|
||||
// x86-64 va_start lowering magic.
|
||||
|
||||
@ -186,6 +186,8 @@ public:
|
||||
/// setup..destroy sequence (e.g. by pushes, or inside the callee).
|
||||
int64_t getFrameAdjustment(const MachineInstr &I) const {
|
||||
assert(isFrameInstr(I));
|
||||
if (isFrameSetup(I))
|
||||
return I.getOperand(2).getImm();
|
||||
return I.getOperand(1).getImm();
|
||||
}
|
||||
|
||||
@ -193,7 +195,10 @@ public:
|
||||
/// instruction.
|
||||
void setFrameAdjustment(MachineInstr &I, int64_t V) const {
|
||||
assert(isFrameInstr(I));
|
||||
I.getOperand(1).setImm(V);
|
||||
if (isFrameSetup(I))
|
||||
I.getOperand(2).setImm(V);
|
||||
else
|
||||
I.getOperand(1).setImm(V);
|
||||
}
|
||||
|
||||
/// getSPAdjust - This returns the stack pointer adjustment made by
|
||||
|
||||
@ -84,7 +84,8 @@ def SDTLockBinaryArithWithFlags : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
|
||||
|
||||
def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>;
|
||||
|
||||
def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
|
||||
def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>,
|
||||
SDTCisVT<1, i32>]>;
|
||||
def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
|
||||
SDTCisVT<1, i32>]>;
|
||||
|
||||
|
||||
@ -1131,8 +1131,7 @@ SDValue XCoreTargetLowering::LowerCCCCallTo(
|
||||
unsigned NumBytes = RetCCInfo.getNextStackOffset();
|
||||
auto PtrVT = getPointerTy(DAG.getDataLayout());
|
||||
|
||||
Chain = DAG.getCALLSEQ_START(Chain,
|
||||
DAG.getConstant(NumBytes, dl, PtrVT, true), dl);
|
||||
Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
|
||||
|
||||
SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
|
||||
SmallVector<SDValue, 12> MemOpChains;
|
||||
|
||||
@ -73,9 +73,10 @@ def XCoreLdwsp : SDNode<"XCoreISD::LDWSP", SDT_XCoreLdwsp,
|
||||
[SDNPHasChain, SDNPMayLoad]>;
|
||||
|
||||
// These are target-independent nodes, but have target-specific formats.
|
||||
def SDT_XCoreCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
|
||||
def SDT_XCoreCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>,
|
||||
SDTCisVT<1, i32> ]>;
|
||||
def SDT_XCoreCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
|
||||
SDTCisVT<1, i32> ]>;
|
||||
SDTCisVT<1, i32> ]>;
|
||||
|
||||
def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_XCoreCallSeqStart,
|
||||
[SDNPHasChain, SDNPOutGlue]>;
|
||||
@ -323,9 +324,9 @@ class F2R_np<bits<6> opc, string OpcStr> :
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
let Defs = [SP], Uses = [SP] in {
|
||||
def ADJCALLSTACKDOWN : PseudoInstXCore<(outs), (ins i32imm:$amt),
|
||||
"# ADJCALLSTACKDOWN $amt",
|
||||
[(callseq_start timm:$amt)]>;
|
||||
def ADJCALLSTACKDOWN : PseudoInstXCore<(outs), (ins i32imm:$amt, i32imm:$amt2),
|
||||
"# ADJCALLSTACKDOWN $amt, $amt2",
|
||||
[(callseq_start timm:$amt, timm:$amt2)]>;
|
||||
def ADJCALLSTACKUP : PseudoInstXCore<(outs), (ins i32imm:$amt1, i32imm:$amt2),
|
||||
"# ADJCALLSTACKUP $amt1",
|
||||
[(callseq_end timm:$amt1, timm:$amt2)]>;
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
; RUN: llc -mtriple=aarch64-linux-gnu -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
|
||||
|
||||
; CHECK-LABEL: name: test_trivial_call
|
||||
; CHECK: ADJCALLSTACKDOWN 0, implicit-def %sp, implicit %sp
|
||||
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def %sp, implicit %sp
|
||||
; CHECK: BL @trivial_callee, csr_aarch64_aapcs, implicit-def %lr
|
||||
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def %sp, implicit %sp
|
||||
declare void @trivial_callee()
|
||||
@ -186,7 +186,7 @@ define void @test_stack_slots([8 x i64], i64 %lhs, i64 %rhs, i64* %addr) {
|
||||
; CHECK: [[C42:%[0-9]+]](s64) = G_CONSTANT i64 42
|
||||
; CHECK: [[C12:%[0-9]+]](s64) = G_CONSTANT i64 12
|
||||
; CHECK: [[PTR:%[0-9]+]](p0) = G_CONSTANT i64 0
|
||||
; CHECK: ADJCALLSTACKDOWN 24, implicit-def %sp, implicit %sp
|
||||
; CHECK: ADJCALLSTACKDOWN 24, 0, implicit-def %sp, implicit %sp
|
||||
; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp
|
||||
; CHECK: [[C42_OFFS:%[0-9]+]](s64) = G_CONSTANT i64 0
|
||||
; CHECK: [[C42_LOC:%[0-9]+]](p0) = G_GEP [[SP]], [[C42_OFFS]](s64)
|
||||
|
||||
@ -7,11 +7,11 @@ entry:
|
||||
store i64 11, i64* %metadata
|
||||
store i64 12, i64* %metadata
|
||||
store i64 13, i64* %metadata
|
||||
; ISEL: ADJCALLSTACKDOWN 0, implicit-def
|
||||
; ISEL: ADJCALLSTACKDOWN 0, 0, implicit-def
|
||||
; ISEL-NEXT: STACKMAP
|
||||
; ISEL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def
|
||||
call void (i64, i32, ...) @llvm.experimental.stackmap(i64 4, i32 0, i64* %metadata)
|
||||
; FAST-ISEL: ADJCALLSTACKDOWN 0, implicit-def
|
||||
; FAST-ISEL: ADJCALLSTACKDOWN 0, 0, implicit-def
|
||||
; FAST-ISEL-NEXT: STACKMAP
|
||||
; FAST-ISEL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def
|
||||
ret void
|
||||
|
||||
@ -421,7 +421,7 @@ entry:
|
||||
define arm_aapcscc void @test_indirect_call(void() *%fptr) {
|
||||
; CHECK-LABEL: name: test_indirect_call
|
||||
; CHECK: [[FPTR:%[0-9]+]](p0) = COPY %r0
|
||||
; CHECK: ADJCALLSTACKDOWN 0, 14, _, implicit-def %sp, implicit %sp
|
||||
; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp
|
||||
; CHECK: BLX [[FPTR]](p0), csr_aapcs, implicit-def %lr, implicit %sp
|
||||
; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp
|
||||
entry:
|
||||
@ -433,7 +433,7 @@ declare arm_aapcscc void @call_target()
|
||||
|
||||
define arm_aapcscc void @test_direct_call() {
|
||||
; CHECK-LABEL: name: test_direct_call
|
||||
; CHECK: ADJCALLSTACKDOWN 0, 14, _, implicit-def %sp, implicit %sp
|
||||
; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp
|
||||
; CHECK: BLX @call_target, csr_aapcs, implicit-def %lr, implicit %sp
|
||||
; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp
|
||||
entry:
|
||||
@ -447,7 +447,7 @@ define arm_aapcscc i32* @test_call_simple_reg_params(i32 *%a, i32 %b) {
|
||||
; CHECK-LABEL: name: test_call_simple_reg_params
|
||||
; CHECK-DAG: [[AVREG:%[0-9]+]](p0) = COPY %r0
|
||||
; CHECK-DAG: [[BVREG:%[0-9]+]](s32) = COPY %r1
|
||||
; CHECK: ADJCALLSTACKDOWN 0, 14, _, implicit-def %sp, implicit %sp
|
||||
; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp
|
||||
; CHECK-DAG: %r0 = COPY [[BVREG]]
|
||||
; CHECK-DAG: %r1 = COPY [[AVREG]]
|
||||
; CHECK: BLX @simple_reg_params_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit-def %r0
|
||||
@ -466,7 +466,7 @@ define arm_aapcscc i32* @test_call_simple_stack_params(i32 *%a, i32 %b) {
|
||||
; CHECK-LABEL: name: test_call_simple_stack_params
|
||||
; CHECK-DAG: [[AVREG:%[0-9]+]](p0) = COPY %r0
|
||||
; CHECK-DAG: [[BVREG:%[0-9]+]](s32) = COPY %r1
|
||||
; CHECK: ADJCALLSTACKDOWN 8, 14, _, implicit-def %sp, implicit %sp
|
||||
; CHECK: ADJCALLSTACKDOWN 8, 0, 14, _, implicit-def %sp, implicit %sp
|
||||
; CHECK-DAG: %r0 = COPY [[BVREG]]
|
||||
; CHECK-DAG: %r1 = COPY [[AVREG]]
|
||||
; CHECK-DAG: %r2 = COPY [[BVREG]]
|
||||
@ -496,7 +496,7 @@ define arm_aapcscc signext i16 @test_call_ext_params(i8 %a, i16 %b, i1 %c) {
|
||||
; CHECK-DAG: [[AVREG:%[0-9]+]](s8) = COPY %r0
|
||||
; CHECK-DAG: [[BVREG:%[0-9]+]](s16) = COPY %r1
|
||||
; CHECK-DAG: [[CVREG:%[0-9]+]](s1) = COPY %r2
|
||||
; CHECK: ADJCALLSTACKDOWN 20, 14, _, implicit-def %sp, implicit %sp
|
||||
; CHECK: ADJCALLSTACKDOWN 20, 0, 14, _, implicit-def %sp, implicit %sp
|
||||
; CHECK: [[SEXTA:%[0-9]+]](s32) = G_SEXT [[AVREG]](s8)
|
||||
; CHECK: %r0 = COPY [[SEXTA]]
|
||||
; CHECK: [[ZEXTA:%[0-9]+]](s32) = G_ZEXT [[AVREG]](s8)
|
||||
@ -547,7 +547,7 @@ define arm_aapcs_vfpcc double @test_call_vfpcc_fp_params(double %a, float %b) {
|
||||
; CHECK-LABEL: name: test_call_vfpcc_fp_params
|
||||
; CHECK-DAG: [[AVREG:%[0-9]+]](s64) = COPY %d0
|
||||
; CHECK-DAG: [[BVREG:%[0-9]+]](s32) = COPY %s2
|
||||
; CHECK: ADJCALLSTACKDOWN 0, 14, _, implicit-def %sp, implicit %sp
|
||||
; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp
|
||||
; CHECK-DAG: %s0 = COPY [[BVREG]]
|
||||
; CHECK-DAG: %d1 = COPY [[AVREG]]
|
||||
; CHECK: BLX @vfpcc_fp_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %s0, implicit %d1, implicit-def %d0
|
||||
@ -569,7 +569,7 @@ define arm_aapcscc double @test_call_aapcs_fp_params(double %a, float %b) {
|
||||
; LITTLE-DAG: [[AVREG:%[0-9]+]](s64) = G_SEQUENCE [[A1]](s32), 0, [[A2]](s32), 32
|
||||
; BIG-DAG: [[AVREG:%[0-9]+]](s64) = G_SEQUENCE [[A2]](s32), 0, [[A1]](s32), 32
|
||||
; CHECK-DAG: [[BVREG:%[0-9]+]](s32) = COPY %r2
|
||||
; CHECK: ADJCALLSTACKDOWN 16, 14, _, implicit-def %sp, implicit %sp
|
||||
; CHECK: ADJCALLSTACKDOWN 16, 0, 14, _, implicit-def %sp, implicit %sp
|
||||
; CHECK-DAG: %r0 = COPY [[BVREG]]
|
||||
; CHECK-DAG: [[A1:%[0-9]+]](s32) = G_EXTRACT [[AVREG]](s64), 0
|
||||
; CHECK-DAG: [[A2:%[0-9]+]](s32) = G_EXTRACT [[AVREG]](s64), 32
|
||||
@ -608,7 +608,7 @@ declare arm_aapcscc float @different_call_conv_target(float)
|
||||
define arm_aapcs_vfpcc float @test_call_different_call_conv(float %x) {
|
||||
; CHECK-LABEL: name: test_call_different_call_conv
|
||||
; CHECK: [[X:%[0-9]+]](s32) = COPY %s0
|
||||
; CHECK: ADJCALLSTACKDOWN 0, 14, _, implicit-def %sp, implicit %sp
|
||||
; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp
|
||||
; CHECK: %r0 = COPY [[X]]
|
||||
; CHECK: BLX @different_call_conv_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit-def %r0
|
||||
; CHECK: [[R:%[0-9]+]](s32) = COPY %r0
|
||||
|
||||
@ -161,17 +161,17 @@ body: |
|
||||
bb.1.for.body:
|
||||
successors: %bb.3.for.end, %bb.2.if.end82
|
||||
|
||||
ADJCALLSTACKDOWN 0, implicit-def dead %r29, implicit-def dead %r30, implicit %r31, implicit %r30, implicit %r29
|
||||
ADJCALLSTACKDOWN 0, 0, implicit-def dead %r29, implicit-def dead %r30, implicit %r31, implicit %r30, implicit %r29
|
||||
J2_call @lrand48, implicit-def dead %d0, implicit-def dead %d1, implicit-def dead %d2, implicit-def dead %d3, implicit-def dead %d4, implicit-def dead %d5, implicit-def dead %d6, implicit-def dead %d7, implicit-def dead %r28, implicit-def dead %r31, implicit-def dead %p0, implicit-def dead %p1, implicit-def dead %p2, implicit-def dead %p3, implicit-def dead %m0, implicit-def dead %m1, implicit-def dead %lc0, implicit-def dead %lc1, implicit-def dead %sa0, implicit-def dead %sa1, implicit-def dead %usr, implicit-def %usr_ovf, implicit-def dead %cs0, implicit-def dead %cs1, implicit-def dead %w0, implicit-def dead %w1, implicit-def dead %w2, implicit-def dead %w3, implicit-def dead %w4, implicit-def dead %w5, implicit-def dead %w6, implicit-def dead %w7, implicit-def dead %w8, implicit-def dead %w9, implicit-def dead %w10, implicit-def dead %w11, implicit-def dead %w12, implicit-def dead %w13, implicit-def dead %w14, implicit-def dead %w15, implicit-def dead %q0, implicit-def dead %q1, implicit-def dead %q2, implicit-def dead %q3, implicit-def %r0
|
||||
ADJCALLSTACKUP 0, 0, implicit-def dead %r29, implicit-def dead %r30, implicit-def dead %r31, implicit %r29
|
||||
undef %29.isub_lo = COPY killed %r0
|
||||
%29.isub_hi = S2_asr_i_r %29.isub_lo, 31
|
||||
ADJCALLSTACKDOWN 0, implicit-def dead %r29, implicit-def dead %r30, implicit %r31, implicit %r30, implicit %r29
|
||||
ADJCALLSTACKDOWN 0, 0, implicit-def dead %r29, implicit-def dead %r30, implicit %r31, implicit %r30, implicit %r29
|
||||
J2_call @lrand48, implicit-def dead %d0, implicit-def dead %d1, implicit-def dead %d2, implicit-def dead %d3, implicit-def dead %d4, implicit-def dead %d5, implicit-def dead %d6, implicit-def dead %d7, implicit-def dead %r28, implicit-def dead %r31, implicit-def dead %p0, implicit-def dead %p1, implicit-def dead %p2, implicit-def dead %p3, implicit-def dead %m0, implicit-def dead %m1, implicit-def dead %lc0, implicit-def dead %lc1, implicit-def dead %sa0, implicit-def dead %sa1, implicit-def dead %usr, implicit-def %usr_ovf, implicit-def dead %cs0, implicit-def dead %cs1, implicit-def dead %w0, implicit-def dead %w1, implicit-def dead %w2, implicit-def dead %w3, implicit-def dead %w4, implicit-def dead %w5, implicit-def dead %w6, implicit-def dead %w7, implicit-def dead %w8, implicit-def dead %w9, implicit-def dead %w10, implicit-def dead %w11, implicit-def dead %w12, implicit-def dead %w13, implicit-def dead %w14, implicit-def dead %w15, implicit-def dead %q0, implicit-def dead %q1, implicit-def dead %q2, implicit-def dead %q3, implicit-def %r0
|
||||
ADJCALLSTACKUP 0, 0, implicit-def dead %r29, implicit-def dead %r30, implicit-def dead %r31, implicit %r29
|
||||
%32.isub_lo = COPY killed %r0
|
||||
%7 = S2_extractup %32, 22, 9
|
||||
ADJCALLSTACKDOWN 0, implicit-def dead %r29, implicit-def dead %r30, implicit %r31, implicit %r30, implicit %r29
|
||||
ADJCALLSTACKDOWN 0, 0, implicit-def dead %r29, implicit-def dead %r30, implicit %r31, implicit %r30, implicit %r29
|
||||
J2_call @lrand48, implicit-def dead %d0, implicit-def dead %d1, implicit-def dead %d2, implicit-def dead %d3, implicit-def dead %d4, implicit-def dead %d5, implicit-def dead %d6, implicit-def dead %d7, implicit-def dead %r28, implicit-def dead %r31, implicit-def dead %p0, implicit-def dead %p1, implicit-def dead %p2, implicit-def dead %p3, implicit-def dead %m0, implicit-def dead %m1, implicit-def dead %lc0, implicit-def dead %lc1, implicit-def dead %sa0, implicit-def dead %sa1, implicit-def dead %usr, implicit-def %usr_ovf, implicit-def dead %cs0, implicit-def dead %cs1, implicit-def dead %w0, implicit-def dead %w1, implicit-def dead %w2, implicit-def dead %w3, implicit-def dead %w4, implicit-def dead %w5, implicit-def dead %w6, implicit-def dead %w7, implicit-def dead %w8, implicit-def dead %w9, implicit-def dead %w10, implicit-def dead %w11, implicit-def dead %w12, implicit-def dead %w13, implicit-def dead %w14, implicit-def dead %w15, implicit-def dead %q0, implicit-def dead %q1, implicit-def dead %q2, implicit-def dead %q3, implicit-def %r0
|
||||
ADJCALLSTACKUP 0, 0, implicit-def dead %r29, implicit-def dead %r30, implicit-def dead %r31, implicit %r29
|
||||
undef %43.isub_lo = COPY killed %r0
|
||||
@ -179,7 +179,7 @@ body: |
|
||||
%16 = S2_extractup %43, 6, 25
|
||||
%18 = A2_tfrpi -1
|
||||
%18 = S2_asl_r_p_acc %18, %47, %16.isub_lo
|
||||
ADJCALLSTACKDOWN 0, implicit-def dead %r29, implicit-def dead %r30, implicit %r31, implicit %r30, implicit %r29
|
||||
ADJCALLSTACKDOWN 0, 0, implicit-def dead %r29, implicit-def dead %r30, implicit %r31, implicit %r30, implicit %r29
|
||||
J2_call @lrand48, implicit-def dead %d0, implicit-def dead %d1, implicit-def dead %d2, implicit-def dead %d3, implicit-def dead %d4, implicit-def dead %d5, implicit-def dead %d6, implicit-def dead %d7, implicit-def dead %r28, implicit-def dead %r31, implicit-def dead %p0, implicit-def dead %p1, implicit-def dead %p2, implicit-def dead %p3, implicit-def dead %m0, implicit-def dead %m1, implicit-def dead %lc0, implicit-def dead %lc1, implicit-def dead %sa0, implicit-def dead %sa1, implicit-def dead %usr, implicit-def %usr_ovf, implicit-def dead %cs0, implicit-def dead %cs1, implicit-def dead %w0, implicit-def dead %w1, implicit-def dead %w2, implicit-def dead %w3, implicit-def dead %w4, implicit-def dead %w5, implicit-def dead %w6, implicit-def dead %w7, implicit-def dead %w8, implicit-def dead %w9, implicit-def dead %w10, implicit-def dead %w11, implicit-def dead %w12, implicit-def dead %w13, implicit-def dead %w14, implicit-def dead %w15, implicit-def dead %q0, implicit-def dead %q1, implicit-def dead %q2, implicit-def dead %q3
|
||||
ADJCALLSTACKUP 0, 0, implicit-def dead %r29, implicit-def dead %r30, implicit-def dead %r31, implicit %r29
|
||||
%22 = S2_asl_r_p %18, %8.isub_lo
|
||||
|
||||
@ -644,7 +644,7 @@ body: |
|
||||
bb.1.if.then:
|
||||
successors: %bb.2.while.body
|
||||
|
||||
ADJCALLSTACKDOWN 0, implicit-def dead %sp, implicit %sp
|
||||
ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
|
||||
CALL @g, csr, implicit-def dead %rca, implicit %sp, implicit-def %sp, implicit-def %rv
|
||||
ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
|
||||
|
||||
@ -663,7 +663,7 @@ body: |
|
||||
bb.4.if.then4:
|
||||
successors: %bb.5.while.body6
|
||||
|
||||
ADJCALLSTACKDOWN 0, implicit-def dead %sp, implicit %sp
|
||||
ADJCALLSTACKDOWN 0, 0, implicit-def dead %sp, implicit %sp
|
||||
CALL @g, csr, implicit-def dead %rca, implicit %sp, implicit-def %sp, implicit-def %rv
|
||||
ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp
|
||||
|
||||
|
||||
@ -60,7 +60,7 @@ body: |
|
||||
liveins: %eax
|
||||
|
||||
MOV32mr %stack.0.tmp, 1, _, 0, _, killed %eax
|
||||
ADJCALLSTACKDOWN64 0, 0, implicit-def %rsp, implicit-def dead %eflags, implicit %rsp
|
||||
ADJCALLSTACKDOWN64 0, 0, 0, implicit-def %rsp, implicit-def dead %eflags, implicit %rsp
|
||||
%rsi = LEA64r %stack.0.tmp, 1, _, 0, _
|
||||
%edi = MOV32r0 implicit-def dead %eflags
|
||||
CALL64pcrel32 @doSomething, csr_64, implicit %rsp, implicit %edi, implicit %rsi, implicit-def %rsp, implicit-def %eax
|
||||
|
||||
@ -7,11 +7,11 @@ entry:
|
||||
store i64 11, i64* %metadata
|
||||
store i64 12, i64* %metadata
|
||||
store i64 13, i64* %metadata
|
||||
; ISEL: ADJCALLSTACKDOWN 0, implicit-def
|
||||
; ISEL: ADJCALLSTACKDOWN 0, 0, implicit-def
|
||||
; ISEL-NEXT: STACKMAP
|
||||
; ISEL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def
|
||||
call void (i64, i32, ...) @llvm.experimental.stackmap(i64 4, i32 0, i64* %metadata)
|
||||
; FAST-ISEL: ADJCALLSTACKDOWN 0, implicit-def
|
||||
; FAST-ISEL: ADJCALLSTACKDOWN 0, 0, implicit-def
|
||||
; FAST-ISEL-NEXT: STACKMAP
|
||||
; FAST-ISEL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def
|
||||
ret void
|
||||
|
||||
@ -7,11 +7,11 @@ entry:
|
||||
store i64 11, i64* %metadata
|
||||
store i64 12, i64* %metadata
|
||||
store i64 13, i64* %metadata
|
||||
; ISEL: ADJCALLSTACKDOWN64 0, 0, implicit-def
|
||||
; ISEL: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def
|
||||
; ISEL-NEXT: STACKMAP
|
||||
; ISEL-NEXT: ADJCALLSTACKUP64 0, 0, implicit-def
|
||||
call void (i64, i32, ...) @llvm.experimental.stackmap(i64 4, i32 0, i64* %metadata)
|
||||
; FAST-ISEL: ADJCALLSTACKDOWN64 0, 0, implicit-def
|
||||
; FAST-ISEL: ADJCALLSTACKDOWN64 0, 0, 0, implicit-def
|
||||
; FAST-ISEL-NEXT: STACKMAP
|
||||
; FAST-ISEL-NEXT: ADJCALLSTACKUP64 0, 0, implicit-def
|
||||
ret void
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user