WebAssembly: start instructions

Summary:
* Add 64-bit address space feature.
* Rename SIMD feature to SIMD128.
* Handle single-thread model with an IR pass (same way ARM does).
* Rename generic processor to MVP, to follow design's lead.
* Add bleeding-edge processors, with all features included.
* Fix a few DEBUG_TYPE to match other backends.

Test Plan: ninja check

Reviewers: sunfish

Subscribers: jfb, llvm-commits

Differential Revision: http://reviews.llvm.org/D10880

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241211 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/WebAssembly/WebAssembly.td

@@ -22,8 +22,8 @@ include "llvm/Target/Target.td"
 // WebAssembly Subtarget features.
 //===----------------------------------------------------------------------===//
 
-def FeatureSIMD : SubtargetFeature<"simd", "HasSIMD", "true",
+def FeatureSIMD128 : SubtargetFeature<"simd128", "HasSIMD128", "false",
-                                   "Enable SIMD">;
+                                      "Enable 128-bit SIMD">;
 
 //===----------------------------------------------------------------------===//
 // Architectures.
@@ -47,7 +47,11 @@ def WebAssemblyInstrInfo : InstrInfo;
 // WebAssembly Processors supported.
 //===----------------------------------------------------------------------===//
 
-def : ProcessorModel<"generic", NoSchedModel, [FeatureSIMD]>;
+// Minimal Viable Product.
+def : ProcessorModel<"mvp", NoSchedModel, []>;
+
+// Latest and greatest experimental version of WebAssembly. Bugs included!
+def : ProcessorModel<"bleeding-edge", NoSchedModel, [FeatureSIMD128]>;
 
 //===----------------------------------------------------------------------===//
 // Target Declaration

lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp

@@ -32,7 +32,7 @@
 #include "llvm/Support/Debug.h"
 using namespace llvm;
 
-#define DEBUG_TYPE "frame-info"
+#define DEBUG_TYPE "wasm-frame-info"
 
 // TODO: Implement a red zone?
 

lib/Target/WebAssembly/WebAssemblyInstrAtomics.td

@@ -11,6 +11,8 @@
 //
 //===----------------------------------------------------------------------===//
 
+// TODO: Implement atomic instructions.
+
 //===----------------------------------------------------------------------===//
 // Atomic fences
 //===----------------------------------------------------------------------===//

lib/Target/WebAssembly/WebAssemblyInstrInfo.td

@@ -15,6 +15,11 @@
 // WebAssembly Instruction Predicate Definitions.
 //===----------------------------------------------------------------------===//
 
+def HasAddr32 : Predicate<"!Subtarget->hasAddr64()">;
+def HasAddr64 : Predicate<"Subtarget->hasAddr64()">;
+def HasSIMD128 : Predicate<"Subtarget->hasSIMD128()">,
+                           AssemblerPredicate<"FeatureSIMD128", "simd128">;
+
 //===----------------------------------------------------------------------===//
 // WebAssembly-specific DAG Node Types.
 //===----------------------------------------------------------------------===//

lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

@@ -12,4 +12,4 @@
 //===----------------------------------------------------------------------===//
 
 // TODO: Implement SIMD instructions.
-// Note: use Requires<[HasSIMD]>.
+// Note: use Requires<[HasSIMD128]>.

lib/Target/WebAssembly/WebAssemblySubtarget.cpp

@@ -19,7 +19,7 @@
 #include "llvm/Support/TargetRegistry.h"
 using namespace llvm;
 
-#define DEBUG_TYPE "subtarget"
+#define DEBUG_TYPE "wasm-subtarget"
 
 #define GET_SUBTARGETINFO_CTOR
 #define GET_SUBTARGETINFO_TARGET_DESC
@@ -40,8 +40,8 @@ WebAssemblySubtarget::WebAssemblySubtarget(const Triple &TT,
                                            const std::string &CPU,
                                            const std::string &FS,
                                            const TargetMachine &TM)
-    : WebAssemblyGenSubtargetInfo(TT, CPU, FS), HasSIMD(true), CPUString(CPU),
+    : WebAssemblyGenSubtargetInfo(TT, CPU, FS), HasSIMD128(false),
-      TargetTriple(TT), FrameLowering(),
+      CPUString(CPU), TargetTriple(TT), FrameLowering(),
       InstrInfo(initializeSubtargetDependencies(FS)),
       TSInfo(TM.getDataLayout()), TLInfo(TM, *this) {}
 

lib/Target/WebAssembly/WebAssemblySubtarget.h

@@ -29,7 +29,7 @@
 namespace llvm {
 
 class WebAssemblySubtarget final : public WebAssemblyGenSubtargetInfo {
-  bool HasSIMD;
+  bool HasSIMD128;
 
   /// String name of used CPU.
   std::string CPUString;
@@ -66,7 +66,8 @@ public:
   bool useAA() const override { return true; }
 
   // Predicates used by WebAssemblyInstrInfo.td.
-  bool hasSIMD() const { return HasSIMD; }
+  bool hasAddr64() const { return TargetTriple.isArch64Bit(); }
+  bool hasSIMD128() const { return HasSIMD128; }
 
   /// Parses features string setting specified subtarget options. Definition of
   /// function is auto generated by tblgen.

lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp

@@ -24,6 +24,7 @@
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Target/TargetOptions.h"
+#include "llvm/Transforms/Scalar.h"
 using namespace llvm;
 
 #define DEBUG_TYPE "wasm"
@@ -139,9 +140,14 @@ void WebAssemblyPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
 //===----------------------------------------------------------------------===//
 
 void WebAssemblyPassConfig::addIRPasses() {
-  // Expand some atomic operations. WebAssemblyTargetLowering has hooks which
+  // FIXME: the default for this option is currently POSIX, whereas
-  // control specifically what gets lowered.
+  // WebAssembly's MVP should default to Single.
-  addPass(createAtomicExpandPass(&getTM<WebAssemblyTargetMachine>()));
+  if (TM->Options.ThreadModel == ThreadModel::Single)
+    addPass(createLowerAtomicPass());
+  else
+    // Expand some atomic operations. WebAssemblyTargetLowering has hooks which
+    // control specifically what gets lowered.
+    addPass(createAtomicExpandPass(TM));
 
   TargetPassConfig::addIRPasses();
 }