RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2024-12-27 22:55:15 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

[SystemZ] Allow integer XOR involving high words

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191759 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Sandiford 2013-10-01 14:08:44 +00:00
parent 8819c84aed
commit 1ff62e182e
5 changed files with 57 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
lib/Target/SystemZ/SystemZAsmPrinter.cpp
View File

@ -130,6 +130,7 @@ void SystemZAsmPrinter::EmitInstruction(const MachineInstr *MI) {
LOWER_HIGH(OIHL); LOWER_HIGH(OIHL);
LOWER_HIGH(OIHH); LOWER_HIGH(OIHH);
LOWER_HIGH(OIHF); LOWER_HIGH(OIHF);
LOWER_HIGH(XIHF);
#undef LOWER_HIGH #undef LOWER_HIGH

4
lib/Target/SystemZ/SystemZISelLowering.cpp
View File

@ -3011,8 +3011,8 @@ EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const {
return emitAtomicLoadBinary(MI, MBB, SystemZ::XGR, 64); return emitAtomicLoadBinary(MI, MBB, SystemZ::XGR, 64);
case SystemZ::ATOMIC_LOAD_XILF64: case SystemZ::ATOMIC_LOAD_XILF64:
return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF64, 64); return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF64, 64);
case SystemZ::ATOMIC_LOAD_XIHF: case SystemZ::ATOMIC_LOAD_XIHF64:
return emitAtomicLoadBinary(MI, MBB, SystemZ::XIHF, 64); return emitAtomicLoadBinary(MI, MBB, SystemZ::XIHF64, 64);
case SystemZ::ATOMIC_LOADW_NRi: case SystemZ::ATOMIC_LOADW_NRi:
return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0, true); return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0, true);

4
lib/Target/SystemZ/SystemZInstrInfo.cpp
View File

@ -901,6 +901,10 @@ SystemZInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
expandRIPseudo(MI, SystemZ::OILH, SystemZ::OIHH, false); expandRIPseudo(MI, SystemZ::OILH, SystemZ::OIHH, false);
return true; return true;
case SystemZ::XIFMux:
expandRIPseudo(MI, SystemZ::XILF, SystemZ::XIHF, false);
return true;
case SystemZ::ADJDYNALLOC: case SystemZ::ADJDYNALLOC:
splitAdjDynAlloc(MI); splitAdjDynAlloc(MI);
return true; return true;

11
lib/Target/SystemZ/SystemZInstrInfo.td
View File

@ -900,10 +900,15 @@ let Defs = [CC] in {
// XORs of a 32-bit immediate, leaving other bits unaffected. // XORs of a 32-bit immediate, leaving other bits unaffected.
// The CC result only reflects the 32-bit field, which means we can // The CC result only reflects the 32-bit field, which means we can
// use it as a zero indicator for i32 operations but not otherwise. // use it as a zero indicator for i32 operations but not otherwise.
let CCValues = 0xC, CompareZeroCCMask = 0x8 in let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
// Expands to XILF or XIHF, depending on the choice of register.
def XIFMux : BinaryRIPseudo<xor, GRX32, uimm32>,
Requires<[FeatureHighWord]>;
def XILF : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>; def XILF : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>;
def XIHF : BinaryRIL<"xihf", 0xC06, xor, GRH32, uimm32>;
}
def XILF64 : BinaryAliasRIL<xor, GR64, imm64lf32>; def XILF64 : BinaryAliasRIL<xor, GR64, imm64lf32>;
def XIHF : BinaryRIL<"xihf", 0xC06, xor, GR64, imm64hf32>; def XIHF64 : BinaryAliasRIL<xor, GR64, imm64hf32>;
// XORs of memory. // XORs of memory.
let CCValues = 0xC, CompareZeroCCMask = 0x8 in { let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
@ -1186,7 +1191,7 @@ def ATOMIC_LOAD_XR : AtomicLoadBinaryReg32<atomic_load_xor_32>;
def ATOMIC_LOAD_XILF : AtomicLoadBinaryImm32<atomic_load_xor_32, uimm32>; def ATOMIC_LOAD_XILF : AtomicLoadBinaryImm32<atomic_load_xor_32, uimm32>;
def ATOMIC_LOAD_XGR : AtomicLoadBinaryReg64<atomic_load_xor_64>; def ATOMIC_LOAD_XGR : AtomicLoadBinaryReg64<atomic_load_xor_64>;
def ATOMIC_LOAD_XILF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64lf32>; def ATOMIC_LOAD_XILF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64lf32>;
def ATOMIC_LOAD_XIHF : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64hf32>; def ATOMIC_LOAD_XIHF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64hf32>;
def ATOMIC_LOADW_NRi : AtomicLoadWBinaryReg<z_atomic_loadw_nand>; def ATOMIC_LOADW_NRi : AtomicLoadWBinaryReg<z_atomic_loadw_nand>;
def ATOMIC_LOADW_NILHi : AtomicLoadWBinaryImm<z_atomic_loadw_nand, def ATOMIC_LOADW_NILHi : AtomicLoadWBinaryImm<z_atomic_loadw_nand,

42
test/CodeGen/SystemZ/asm-18.ll
View File

@ -395,3 +395,45 @@ define void @f18() {
call void asm sideeffect "stepd $0", "r"(i32 %or3) call void asm sideeffect "stepd $0", "r"(i32 %or3)
ret void ret void
} }
; Test immediate XOR involving high registers.
define void @f19() {
; CHECK-LABEL: f19:
; CHECK: stepa [[REG:%r[0-5]]]
; CHECK: xihf [[REG]], 305397760
; CHECK: stepb [[REG]]
; CHECK: xihf [[REG]], 34661
; CHECK: stepc [[REG]]
; CHECK: xihf [[REG]], 12345678
; CHECK: stepd [[REG]]
; CHECK: br %r14
%res1 = call i32 asm "stepa $0", "=h"()
%xor1 = xor i32 %res1, 305397760
%res2 = call i32 asm "stepb $0, $1", "=h,h"(i32 %xor1)
%xor2 = xor i32 %res2, 34661
%res3 = call i32 asm "stepc $0, $1", "=h,h"(i32 %xor2)
%xor3 = xor i32 %res3, 12345678
call void asm sideeffect "stepd $0", "h"(i32 %xor3)
ret void
}
; Test immediate XOR involving low registers.
define void @f20() {
; CHECK-LABEL: f20:
; CHECK: stepa [[REG:%r[0-5]]]
; CHECK: xilf [[REG]], 305397760
; CHECK: stepb [[REG]]
; CHECK: xilf [[REG]], 34661
; CHECK: stepc [[REG]]
; CHECK: xilf [[REG]], 12345678
; CHECK: stepd [[REG]]
; CHECK: br %r14
%res1 = call i32 asm "stepa $0", "=r"()
%xor1 = xor i32 %res1, 305397760
%res2 = call i32 asm "stepb $0, $1", "=r,r"(i32 %xor1)
%xor2 = xor i32 %res2, 34661
%res3 = call i32 asm "stepc $0, $1", "=r,r"(i32 %xor2)
%xor3 = xor i32 %res3, 12345678
call void asm sideeffect "stepd $0", "r"(i32 %xor3)
ret void
}