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Fix the opcode and the operands for the load instruction.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111885 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2010-08-24 01:10:04 +00:00
parent f06f309002
commit 2012c7bb7b
1 changed files with 5 additions and 2 deletions
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7
lib/Target/ARM/ARMFastISel.cpp
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@ -415,10 +415,13 @@ bool ARMFastISel::ARMSelectLoad(const Instruction *I) {
}
// FIXME: There is more than one register class in the world...
// TODO: Verify the additions above work, otherwise we'll need to add the
// offset instead of 0 and do all sorts of operand munging.
unsigned ResultReg = createResultReg(FixedRC);
unsigned Opc = AFI->isThumb2Function() ? ARM::tLDR : ARM::LDR;
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(ARM::LDR), ResultReg)
.addImm(0).addReg(Reg).addImm(Offset));
TII.get(Opc), ResultReg)
.addReg(Reg).addReg(0).addImm(0));
UpdateValueMap(I, ResultReg);
return true;