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[FastISel][X86] Lower unsupported selects to control-flow.
The extends the select lowering coverage by emiting pseudo cmov instructions. These insturction will be later on lowered to control-flow to simulate the select. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211545 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Juergen Ributzka
parent
d0976a3d20
commit
20732d55c2
@ -115,6 +115,8 @@ private:
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bool X86FastEmitSSESelect(const Instruction *I);
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bool X86FastEmitPseudoSelect(const Instruction *I);
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bool X86SelectSelect(const Instruction *I);
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bool X86SelectTrunc(const Instruction *I);
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@ -1852,6 +1854,70 @@ bool X86FastISel::X86FastEmitSSESelect(const Instruction *I) {
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return true;
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}
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bool X86FastISel::X86FastEmitPseudoSelect(const Instruction *I) {
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MVT RetVT;
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if (!isTypeLegal(I->getType(), RetVT))
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return false;
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// These are pseudo CMOV instructions and will be later expanded into control-
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// flow.
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unsigned Opc;
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switch (RetVT.SimpleTy) {
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default: return false;
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case MVT::i8: Opc = X86::CMOV_GR8; break;
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case MVT::i16: Opc = X86::CMOV_GR16; break;
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case MVT::i32: Opc = X86::CMOV_GR32; break;
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case MVT::f32: Opc = X86::CMOV_FR32; break;
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case MVT::f64: Opc = X86::CMOV_FR64; break;
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}
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const Value *Cond = I->getOperand(0);
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X86::CondCode CC = X86::COND_NE;
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// Don't emit a test if the condition comes from a compare.
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if (const auto *CI = dyn_cast<CmpInst>(Cond)) {
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bool NeedSwap;
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std::tie(CC, NeedSwap) = getX86ConditonCode(CI->getPredicate());
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if (CC > X86::LAST_VALID_COND)
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return false;
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const Value *CmpLHS = CI->getOperand(0);
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const Value *CmpRHS = CI->getOperand(1);
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if (NeedSwap)
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std::swap(CmpLHS, CmpRHS);
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EVT CmpVT = TLI.getValueType(CmpLHS->getType());
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if (!X86FastEmitCompare(CmpLHS, CmpRHS, CmpVT))
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return false;
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} else {
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unsigned CondReg = getRegForValue(Cond);
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if (CondReg == 0)
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return false;
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bool CondIsKill = hasTrivialKill(Cond);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::TEST8ri))
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.addReg(CondReg, getKillRegState(CondIsKill)).addImm(1);
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}
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const Value *LHS = I->getOperand(1);
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const Value *RHS = I->getOperand(2);
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unsigned LHSReg = getRegForValue(LHS);
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bool LHSIsKill = hasTrivialKill(LHS);
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unsigned RHSReg = getRegForValue(RHS);
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bool RHSIsKill = hasTrivialKill(RHS);
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if (!LHSReg || !RHSReg)
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return false;
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const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT);
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unsigned ResultReg =
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FastEmitInst_rri(Opc, RC, RHSReg, RHSIsKill, LHSReg, LHSIsKill, CC);
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UpdateValueMap(I, ResultReg);
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return true;
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}
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bool X86FastISel::X86SelectSelect(const Instruction *I) {
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MVT RetVT;
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if (!isTypeLegal(I->getType(), RetVT))
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@ -1890,6 +1956,11 @@ bool X86FastISel::X86SelectSelect(const Instruction *I) {
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if (X86FastEmitSSESelect(I))
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return true;
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// Fall-back to pseudo conditional move instructions, which will be later
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// converted to control-flow.
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if (X86FastEmitPseudoSelect(I))
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return true;
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return false;
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}
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138
test/CodeGen/X86/fast-isel-select-pseudo-cmov.ll
Normal file
138
test/CodeGen/X86/fast-isel-select-pseudo-cmov.ll
Normal file
@ -0,0 +1,138 @@
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; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -mcpu=corei7-avx | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort -mcpu=corei7-avx | FileCheck %s
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define float @select_fcmp_one_f32(float %a, float %b, float %c, float %d) {
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; CHECK-LABEL: select_fcmp_one_f32
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; CHECK: ucomiss %xmm1, %xmm0
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; CHECK-NEXT: jne [[BB:LBB[0-9]+_2]]
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; CHECK: [[BB]]
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; CHECK-NEXT: movaps %xmm2, %xmm0
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%1 = fcmp one float %a, %b
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%2 = select i1 %1, float %c, float %d
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ret float %2
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}
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define double @select_fcmp_one_f64(double %a, double %b, double %c, double %d) {
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; CHECK-LABEL: select_fcmp_one_f64
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; CHECK: ucomisd %xmm1, %xmm0
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; CHECK-NEXT: jne [[BB:LBB[0-9]+_2]]
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; CHECK: [[BB]]
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; CHECK-NEXT: movaps %xmm2, %xmm0
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%1 = fcmp one double %a, %b
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%2 = select i1 %1, double %c, double %d
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ret double %2
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}
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define float @select_icmp_eq_f32(i64 %a, i64 %b, float %c, float %d) {
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; CHECK-LABEL: select_icmp_eq_f32
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; CHECK: cmpq %rsi, %rdi
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; CHECK-NEXT: je [[BB:LBB[0-9]+_2]]
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; CHECK: [[BB]]
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; CHECK-NEXT: retq
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%1 = icmp eq i64 %a, %b
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%2 = select i1 %1, float %c, float %d
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ret float %2
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}
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define float @select_icmp_ne_f32(i64 %a, i64 %b, float %c, float %d) {
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; CHECK-LABEL: select_icmp_ne_f32
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; CHECK: cmpq %rsi, %rdi
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; CHECK-NEXT: jne [[BB:LBB[0-9]+_2]]
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; CHECK: [[BB]]
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; CHECK-NEXT: retq
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%1 = icmp ne i64 %a, %b
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%2 = select i1 %1, float %c, float %d
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ret float %2
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}
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define float @select_icmp_ugt_f32(i64 %a, i64 %b, float %c, float %d) {
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; CHECK-LABEL: select_icmp_ugt_f32
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; CHECK: cmpq %rsi, %rdi
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; CHECK-NEXT: ja [[BB:LBB[0-9]+_2]]
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; CHECK: [[BB]]
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; CHECK-NEXT: retq
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%1 = icmp ugt i64 %a, %b
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%2 = select i1 %1, float %c, float %d
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ret float %2
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}
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define float @select_icmp_uge_f32(i64 %a, i64 %b, float %c, float %d) {
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; CHECK-LABEL: select_icmp_uge_f32
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; CHECK: cmpq %rsi, %rdi
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; CHECK-NEXT: jae [[BB:LBB[0-9]+_2]]
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; CHECK: [[BB]]
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; CHECK-NEXT: retq
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%1 = icmp uge i64 %a, %b
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%2 = select i1 %1, float %c, float %d
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ret float %2
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}
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define float @select_icmp_ult_f32(i64 %a, i64 %b, float %c, float %d) {
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; CHECK-LABEL: select_icmp_ult_f32
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; CHECK: cmpq %rsi, %rdi
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; CHECK-NEXT: jb [[BB:LBB[0-9]+_2]]
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; CHECK: [[BB]]
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; CHECK-NEXT: retq
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%1 = icmp ult i64 %a, %b
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%2 = select i1 %1, float %c, float %d
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ret float %2
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}
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define float @select_icmp_ule_f32(i64 %a, i64 %b, float %c, float %d) {
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; CHECK-LABEL: select_icmp_ule_f32
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; CHECK: cmpq %rsi, %rdi
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; CHECK-NEXT: jbe [[BB:LBB[0-9]+_2]]
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; CHECK: [[BB]]
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; CHECK-NEXT: retq
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%1 = icmp ule i64 %a, %b
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%2 = select i1 %1, float %c, float %d
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ret float %2
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}
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define float @select_icmp_sgt_f32(i64 %a, i64 %b, float %c, float %d) {
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; CHECK-LABEL: select_icmp_sgt_f32
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; CHECK: cmpq %rsi, %rdi
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; CHECK-NEXT: jg [[BB:LBB[0-9]+_2]]
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; CHECK: [[BB]]
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; CHECK-NEXT: retq
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%1 = icmp sgt i64 %a, %b
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%2 = select i1 %1, float %c, float %d
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ret float %2
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}
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define float @select_icmp_sge_f32(i64 %a, i64 %b, float %c, float %d) {
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; CHECK-LABEL: select_icmp_sge_f32
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; CHECK: cmpq %rsi, %rdi
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; CHECK-NEXT: jge [[BB:LBB[0-9]+_2]]
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; CHECK: [[BB]]
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; CHECK-NEXT: retq
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%1 = icmp sge i64 %a, %b
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%2 = select i1 %1, float %c, float %d
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ret float %2
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}
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define float @select_icmp_slt_f32(i64 %a, i64 %b, float %c, float %d) {
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; CHECK-LABEL: select_icmp_slt_f32
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; CHECK: cmpq %rsi, %rdi
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; CHECK-NEXT: jl [[BB:LBB[0-9]+_2]]
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; CHECK: [[BB]]
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; CHECK-NEXT: retq
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%1 = icmp slt i64 %a, %b
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%2 = select i1 %1, float %c, float %d
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ret float %2
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}
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define float @select_icmp_sle_f32(i64 %a, i64 %b, float %c, float %d) {
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; CHECK-LABEL: select_icmp_sle_f32
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; CHECK: cmpq %rsi, %rdi
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; CHECK-NEXT: jle [[BB:LBB[0-9]+_2]]
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; CHECK: [[BB]]
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; CHECK-NEXT: retq
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%1 = icmp sle i64 %a, %b
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%2 = select i1 %1, float %c, float %d
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ret float %2
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}
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