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fold sext_in_reg, sext_in_reg where both have the same VT. This was

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popping up in Fourinarow.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23722 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman 2005-10-14 01:29:07 +00:00
parent b4871ad694
commit 216def8ecf
1 changed files with 1 additions and 1 deletions
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2
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -1330,7 +1330,7 @@ SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
}
// fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt1
if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
cast<VTSDNode>(N0.getOperand(1))->getVT() < EVT) {
cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) {
return N0;
}
// fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2