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Add support for 64-bit arguments

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24792 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-12-17 20:59:06 +00:00
parent 9a60ff654a
commit 217aabf89e
2 changed files with 24 additions and 0 deletions
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12
lib/Target/Sparc/SparcISelDAGToDAG.cpp
View File

@ -102,6 +102,18 @@ SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
}
ArgValues.push_back(Arg);
break;
}
case MVT::i64: {
unsigned VRegLo = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
MF.addLiveIn(GPR[ArgNo++], VRegLo);
unsigned VRegHi = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
MF.addLiveIn(GPR[ArgNo++], VRegHi);
SDOperand ArgLo = DAG.getCopyFromReg(DAG.getRoot(), VRegLo, MVT::i32);
SDOperand ArgHi = DAG.getCopyFromReg(ArgLo.getValue(1), VRegHi, MVT::i32);
DAG.setRoot(ArgHi.getValue(1));
ArgValues.push_back(DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgLo, ArgHi));
break;
}
}
}

12
lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
View File

@ -102,6 +102,18 @@ SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
}
ArgValues.push_back(Arg);
break;
}
case MVT::i64: {
unsigned VRegLo = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
MF.addLiveIn(GPR[ArgNo++], VRegLo);
unsigned VRegHi = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
MF.addLiveIn(GPR[ArgNo++], VRegHi);
SDOperand ArgLo = DAG.getCopyFromReg(DAG.getRoot(), VRegLo, MVT::i32);
SDOperand ArgHi = DAG.getCopyFromReg(ArgLo.getValue(1), VRegHi, MVT::i32);
DAG.setRoot(ArgHi.getValue(1));
ArgValues.push_back(DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgLo, ArgHi));
break;
}
}
}