RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2024-12-26 14:15:53 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

R600: Expand mad24 for GPUs without it

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209457 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2014-05-22 18:00:20 +00:00
parent f49da4338a
commit 21851f9adb
6 changed files with 38 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
lib/Target/R600/AMDGPUInstructions.td
View File

@ -433,6 +433,16 @@ class UMad24Pat<Instruction Inst> : Pat <
(Inst $src0, $src1, $src2)
>;
class IMad24ExpandPat<Instruction MulInst, Instruction AddInst> : Pat <
(AMDGPUmad_i24 i32:$src0, i32:$src1, i32:$src2),
(AddInst (MulInst $src0, $src1), $src2)
>;
class UMad24ExpandPat<Instruction MulInst, Instruction AddInst> : Pat <
(AMDGPUmad_u24 i32:$src0, i32:$src1, i32:$src2),
(AddInst (MulInst $src0, $src1), $src2)
>;
include "R600Instructions.td"
include "R700Instructions.td"

1
lib/Target/R600/CaymanInstructions.td
View File

@ -49,6 +49,7 @@ def COS_cm : COS_Common<0x8E>;
def : POW_Common <LOG_IEEE_cm, EXP_IEEE_cm, MUL>;
defm DIV_cm : DIV_Common<RECIP_IEEE_cm>;
def : UMad24ExpandPat<MULLO_UINT_cm, ADD_INT>;
// RECIP_UINT emulation for Cayman
// The multiplication scales from [0,1] to the unsigned integer range

8
lib/Target/R600/EvergreenInstructions.td
View File

@ -75,6 +75,9 @@ def COS_eg : COS_Common<0x8E>;
def : POW_Common <LOG_IEEE_eg, EXP_IEEE_eg, MUL>;
def : Pat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_eg $src))>;
def : IMad24ExpandPat<MULLO_INT_eg, ADD_INT>;
def : UMad24ExpandPat<MULLO_UINT_eg, ADD_INT>;
//===----------------------------------------------------------------------===//
// Memory read/write instructions
//===----------------------------------------------------------------------===//
@ -301,8 +304,11 @@ def BFM_INT_eg : R600_2OP <0xA0, "BFM_INT",
>;
def MULADD_UINT24_eg : R600_3OP <0x10, "MULADD_UINT24",
[(set i32:$dst, (add (AMDGPUmul_u24 i32:$src0, i32:$src1), i32:$src2))], VecALU
[(set i32:$dst, (AMDGPUmad_u24 i32:$src0, i32:$src1, i32:$src2))], VecALU
>;
def : UMad24Pat<MULADD_UINT24_eg>;
def BIT_ALIGN_INT_eg : R600_3OP <0xC, "BIT_ALIGN_INT", [], VecALU>;
def : ROTRPattern <BIT_ALIGN_INT_eg>;
def MULADD_eg : MULADD_Common<0x14>;

6
lib/Target/R600/R600Instructions.td
View File

@ -1625,6 +1625,12 @@ def : DwordAddrPat <i32, R600_Reg32>;
} // End isR600toCayman Predicate
let Predicates = [isR600] in {
// Intrinsic patterns
def : IMad24ExpandPat<MULLO_INT_r600, ADD_INT>;
def : UMad24ExpandPat<MULLO_UINT_r600, ADD_INT>;
} // End isR600
def getLDSNoRetOp : InstrMapping {
let FilterClass = "R600_LDS_1A1D";
let RowFields = ["BaseOp"];

7
test/CodeGen/R600/llvm.AMDGPU.imad24.ll
View File

@ -1,11 +1,18 @@
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=CM -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
; XUN: llc -march=r600 -mcpu=r600 -verify-machineinstrs < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
; XUN: llc -march=r600 -mcpu=r770 -verify-machineinstrs < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
; FIXME: Store of i32 seems to be broken pre-EG somehow?
declare i32 @llvm.AMDGPU.imad24(i32, i32, i32) nounwind readnone
; FUNC-LABEL: @test_imad24
; SI: V_MAD_I32_I24
; CM: MULADD_INT24
; R600: MULLO_INT
; R600: ADD_INT
define void @test_imad24(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i32 %src2) nounwind {
%mad = call i32 @llvm.AMDGPU.imad24(i32 %src0, i32 %src1, i32 %src2) nounwind readnone
store i32 %mad, i32 addrspace(1)* %out, align 4

7
test/CodeGen/R600/llvm.AMDGPU.umad24.ll
View File

@ -1,9 +1,16 @@
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; XUN: llc -march=r600 -mcpu=r600 -verify-machineinstrs < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
; XUN: llc -march=r600 -mcpu=rv770 -verify-machineinstrs < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
declare i32 @llvm.AMDGPU.umad24(i32, i32, i32) nounwind readnone
; FUNC-LABEL: @test_umad24
; SI: V_MAD_U32_U24
; EG: MULADD_UINT24
; R600: MULLO_UINT
; R600: ADD_INT
define void @test_umad24(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i32 %src2) nounwind {
%mad = call i32 @llvm.AMDGPU.umad24(i32 %src0, i32 %src1, i32 %src2) nounwind readnone
store i32 %mad, i32 addrspace(1)* %out, align 4