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ARM: Use "dmb sy" for barriers on M-class CPUs

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The usual default of "dmb ish" (inner-shareable) isn't even a valid instruction
on v6M or v7M (well, it does the same thing but software is strongly
discouraged from using it) so we should emit a full-system barrier there.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189483 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover 2013-08-28 14:39:19 +00:00
parent bafb5f8d9f
commit 22266c1d48
2 changed files with 5 additions and 2 deletions
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5
lib/Target/ARM/ARMISelLowering.cpp
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@ -2600,7 +2600,10 @@ static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1));
AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue());
unsigned Domain = ARM_MB::ISH;
if (Subtarget->isSwift() && Ord == Release) {
if (Subtarget->isMClass()) {
// Only a full system barrier exists in the M-class architectures.
Domain = ARM_MB::SY;
} else if (Subtarget->isSwift() && Ord == Release) {
// Swift happens to implement ISHST barriers in a way that's compatible with
// Release semantics but weaker than ISH so we'd be fools not to use
// it. Beware: other processors probably don't!

2
test/CodeGen/Thumb/barrier.ll
View File

@ -7,7 +7,7 @@ define void @t1() {
; V6: blx {{_*}}sync_synchronize
; V6M-LABEL: t1:
; V6M: dmb ish
; V6M: dmb sy
fence seq_cst
ret void
}