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[Hexagon] Create vcombine in HexagonCopyToCombine
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279067 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Krzysztof Parzyszek
parent
94dd772827
commit
22850ef9c5
@ -11,13 +11,9 @@
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// to move them together. If we can move them next to each other we do so and
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// replace them with a combine instruction.
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//===----------------------------------------------------------------------===//
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#include "llvm/PassSupport.h"
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#include "Hexagon.h"
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#include "HexagonInstrInfo.h"
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#include "HexagonMachineFunctionInfo.h"
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#include "HexagonRegisterInfo.h"
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#include "HexagonSubtarget.h"
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#include "HexagonTargetMachine.h"
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#include "llvm/PassSupport.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/DenseSet.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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@ -64,6 +60,7 @@ namespace {
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class HexagonCopyToCombine : public MachineFunctionPass {
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const HexagonInstrInfo *TII;
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const TargetRegisterInfo *TRI;
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const HexagonSubtarget *ST;
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bool ShouldCombineAggressively;
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DenseSet<MachineInstr *> PotentiallyNewifiableTFR;
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@ -163,6 +160,10 @@ static bool isCombinableInstType(MachineInstr &MI, const HexagonInstrInfo *TII,
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(ShouldCombineAggressively || NotExt);
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}
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case Hexagon::V6_vassign:
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case Hexagon::V6_vassign_128B:
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return true;
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default:
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break;
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}
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@ -186,11 +187,22 @@ static bool areCombinableOperations(const TargetRegisterInfo *TRI,
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MachineInstr &LowRegInst, bool AllowC64) {
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unsigned HiOpc = HighRegInst.getOpcode();
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unsigned LoOpc = LowRegInst.getOpcode();
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(void)HiOpc; // Fix compiler warning
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(void)LoOpc; // Fix compiler warning
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assert((HiOpc == Hexagon::A2_tfr || HiOpc == Hexagon::A2_tfrsi) &&
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(LoOpc == Hexagon::A2_tfr || LoOpc == Hexagon::A2_tfrsi) &&
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"Assume individual instructions are of a combinable type");
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auto verifyOpc = [](unsigned Opc) -> void {
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switch (Opc) {
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case Hexagon::A2_tfr:
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case Hexagon::A2_tfrsi:
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case Hexagon::V6_vassign:
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break;
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default:
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llvm_unreachable("Unexpected opcode");
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}
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};
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verifyOpc(HiOpc);
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verifyOpc(LoOpc);
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if (HiOpc == Hexagon::V6_vassign || LoOpc == Hexagon::V6_vassign)
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return HiOpc == LoOpc;
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if (!AllowC64) {
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// There is no combine of two constant extended values.
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@ -216,9 +228,13 @@ static bool areCombinableOperations(const TargetRegisterInfo *TRI,
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}
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static bool isEvenReg(unsigned Reg) {
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assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
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Hexagon::IntRegsRegClass.contains(Reg));
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return (Reg - Hexagon::R0) % 2 == 0;
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assert(TargetRegisterInfo::isPhysicalRegister(Reg));
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if (Hexagon::IntRegsRegClass.contains(Reg))
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return (Reg - Hexagon::R0) % 2 == 0;
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if (Hexagon::VectorRegsRegClass.contains(Reg) ||
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Hexagon::VectorRegs128BRegClass.contains(Reg))
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return (Reg - Hexagon::V0) % 2 == 0;
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llvm_unreachable("Invalid register");
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}
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static void removeKillInfo(MachineInstr &MI, unsigned RegNotKilled) {
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@ -446,8 +462,9 @@ bool HexagonCopyToCombine::runOnMachineFunction(MachineFunction &MF) {
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bool HasChanged = false;
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// Get target info.
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TRI = MF.getSubtarget().getRegisterInfo();
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TII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
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ST = &MF.getSubtarget<HexagonSubtarget>();
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TRI = ST->getRegisterInfo();
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TII = ST->getInstrInfo();
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const Function *F = MF.getFunction();
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bool OptForSize = F->hasFnAttribute(Attribute::OptimizeForSize);
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@ -566,10 +583,19 @@ void HexagonCopyToCombine::combine(MachineInstr &I1, MachineInstr &I2,
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bool IsI1Loreg = (I2DestReg - I1DestReg) == 1;
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unsigned LoRegDef = IsI1Loreg ? I1DestReg : I2DestReg;
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const TargetRegisterClass *SuperRC = nullptr;
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if (Hexagon::IntRegsRegClass.contains(LoRegDef)) {
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SuperRC = &Hexagon::DoubleRegsRegClass;
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} else if (Hexagon::VectorRegsRegClass.contains(LoRegDef)) {
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assert(ST->useHVXOps());
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if (ST->useHVXSglOps())
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SuperRC = &Hexagon::VecDblRegsRegClass;
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else
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SuperRC = &Hexagon::VecDblRegs128BRegClass;
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}
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// Get the double word register.
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unsigned DoubleRegDest =
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TRI->getMatchingSuperReg(LoRegDef, Hexagon::subreg_loreg,
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&Hexagon::DoubleRegsRegClass);
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TRI->getMatchingSuperReg(LoRegDef, Hexagon::subreg_loreg, SuperRC);
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assert(DoubleRegDest != 0 && "Expect a valid register");
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@ -838,7 +864,19 @@ void HexagonCopyToCombine::emitCombineRR(MachineBasicBlock::iterator &InsertPt,
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// Insert new combine instruction.
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// DoubleRegDest = combine HiReg, LoReg
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BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combinew), DoubleDestReg)
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unsigned NewOpc;
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if (Hexagon::DoubleRegsRegClass.contains(DoubleDestReg)) {
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NewOpc = Hexagon::A2_combinew;
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} else if (Hexagon::VecDblRegsRegClass.contains(DoubleDestReg)) {
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assert(ST->useHVXOps());
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if (ST->useHVXSglOps())
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NewOpc = Hexagon::V6_vcombine;
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else
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NewOpc = Hexagon::V6_vcombine_128B;
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} else
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llvm_unreachable("Unexpected register");
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BuildMI(*BB, InsertPt, DL, TII->get(NewOpc), DoubleDestReg)
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.addReg(HiReg, HiRegKillFlag)
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.addReg(LoReg, LoRegKillFlag);
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}
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56
test/CodeGen/Hexagon/vassign-to-combine.ll
Normal file
56
test/CodeGen/Hexagon/vassign-to-combine.ll
Normal file
@ -0,0 +1,56 @@
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; RUN: llc -march=hexagon < %s | FileCheck %s
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; This testcase is known to generate an opportunity for creating vcombine
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; in HexagonCopyToCombine.
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; CHECK: vcombine
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target triple = "hexagon-unknown--elf"
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declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #0
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declare <32 x i32> @llvm.hexagon.V6.vabsdiffuh.128B(<32 x i32>, <32 x i32>) #0
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declare <32 x i32> @llvm.hexagon.V6.vlalignbi.128B(<32 x i32>, <32 x i32>, i32) #0
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declare <32 x i32> @llvm.hexagon.V6.vsathub.128B(<32 x i32>, <32 x i32>) #0
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declare <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32>, <64 x i32>) #0
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declare <64 x i32> @llvm.hexagon.V6.vadduhsat.dv.128B(<64 x i32>, <64 x i32>) #0
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declare <64 x i32> @llvm.hexagon.V6.vaddubh.128B(<32 x i32>, <32 x i32>) #0
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declare <64 x i32> @llvm.hexagon.V6.vmpyub.128B(<32 x i32>, i32) #0
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define void @foo() local_unnamed_addr #1 {
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entry:
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%0 = load <32 x i32>, <32 x i32>* undef, align 128
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%1 = load <32 x i32>, <32 x i32>* null, align 128
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br i1 undef, label %b2, label %b1
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b1: ; preds = %entry
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%2 = tail call <32 x i32> @llvm.hexagon.V6.vlalignbi.128B(<32 x i32> %0, <32 x i32> %1, i32 1)
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%3 = tail call <64 x i32> @llvm.hexagon.V6.vmpyub.128B(<32 x i32> %2, i32 33686018) #1
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%4 = tail call <64 x i32> @llvm.hexagon.V6.vadduhsat.dv.128B(<64 x i32> undef, <64 x i32> %3) #1
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%5 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %4)
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%6 = tail call <32 x i32> @llvm.hexagon.V6.vabsdiffuh.128B(<32 x i32> %5, <32 x i32> undef) #1
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%7 = tail call <64 x i32> @llvm.hexagon.V6.vaddubh.128B(<32 x i32> %6, <32 x i32> undef)
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%8 = tail call <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32> undef, <64 x i32> %7) #1
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%9 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %8) #1
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%10 = tail call <32 x i32> @llvm.hexagon.V6.vsathub.128B(<32 x i32> %9, <32 x i32> undef) #1
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store <32 x i32> %10, <32 x i32>* undef, align 128
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br label %b2
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b2: ; preds = %b1, %entry
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%c2.host31.sroa.3.2.unr.ph = phi <32 x i32> [ zeroinitializer, %b1 ], [ %0, %entry ]
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%c2.host31.sroa.0.2.unr.ph = phi <32 x i32> [ %0, %b1 ], [ %1, %entry ]
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%11 = tail call <32 x i32> @llvm.hexagon.V6.vlalignbi.128B(<32 x i32> %c2.host31.sroa.3.2.unr.ph, <32 x i32> %c2.host31.sroa.0.2.unr.ph, i32 1)
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%12 = tail call <64 x i32> @llvm.hexagon.V6.vmpyub.128B(<32 x i32> %11, i32 33686018) #1
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%13 = tail call <64 x i32> @llvm.hexagon.V6.vadduhsat.dv.128B(<64 x i32> undef, <64 x i32> %12) #1
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%14 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %13)
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%15 = tail call <32 x i32> @llvm.hexagon.V6.vabsdiffuh.128B(<32 x i32> %14, <32 x i32> undef) #1
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%16 = tail call <64 x i32> @llvm.hexagon.V6.vaddubh.128B(<32 x i32> %15, <32 x i32> undef)
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%17 = tail call <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32> undef, <64 x i32> %16) #1
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%18 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %17) #1
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%19 = tail call <32 x i32> @llvm.hexagon.V6.vsathub.128B(<32 x i32> %18, <32 x i32> undef) #1
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store <32 x i32> %19, <32 x i32>* undef, align 128
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ret void
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}
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" }
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