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AMDGPU: Fix copies from physical registers in SIFixSGPRCopies

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This would assert when there were multiple defs of
a physical register.

We just need to move all of the users of it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301730 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2017-04-29 01:26:34 +00:00
parent 40d2ca9f43
commit 23450e5997
2 changed files with 23 additions and 4 deletions
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13
lib/Target/AMDGPU/SIFixSGPRCopies.cpp
View File

@ -278,8 +278,7 @@ static bool phiHasBreakDef(const MachineInstr &PHI,
Visited.insert(Reg);
MachineInstr *DefInstr = MRI.getUniqueVRegDef(Reg);
assert(DefInstr);
MachineInstr *DefInstr = MRI.getVRegDef(Reg);
switch (DefInstr->getOpcode()) {
default:
break;
@ -346,7 +345,7 @@ bool searchPredecessors(const MachineBasicBlock *MBB,
return false;
DenseSet<const MachineBasicBlock*> Visited;
SmallVector<MachineBasicBlock*, 4> Worklist(MBB->pred_begin(),
SmallVector<MachineBasicBlock*, 4> Worklist(MBB->pred_begin(),
MBB->pred_end());
while (!Worklist.empty()) {
@ -546,7 +545,13 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) {
const TargetRegisterClass *SrcRC, *DstRC;
std::tie(SrcRC, DstRC) = getCopyRegClasses(MI, *TRI, MRI);
if (isVGPRToSGPRCopy(SrcRC, DstRC, *TRI)) {
MachineInstr *DefMI = MRI.getVRegDef(MI.getOperand(1).getReg());
unsigned SrcReg = MI.getOperand(1).getReg();
if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
TII->moveToVALU(MI);
break;
}
MachineInstr *DefMI = MRI.getVRegDef(SrcReg);
unsigned SMovOp;
int64_t Imm;
// If we are just copying an immediate, we can replace the copy with

14
test/CodeGen/AMDGPU/inline-asm.ll
View File

@ -232,3 +232,17 @@ entry:
call void asm sideeffect "; use $0 $1 ", "{VGPR0}, {VGPR1}"(i1 %val0, i1 %val1)
ret void
}
; CHECK-LABEL: {{^}}muliple_def_phys_vgpr:
; CHECK: ; def v0
; CHECK: v_mov_b32_e32 v1, v0
; CHECK: ; def v0
; CHECK: v_lshlrev_b32_e32 v{{[0-9]+}}, v0, v1
define amdgpu_kernel void @muliple_def_phys_vgpr() {
entry:
%def0 = call i32 asm sideeffect "; def $0 ", "={VGPR0}"()
%def1 = call i32 asm sideeffect "; def $0 ", "={VGPR0}"()
%add = shl i32 %def0, %def1
store i32 %add, i32 addrspace(1)* undef
ret void
}