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[Hexagon] Fixing 224952 where an addressing mode update was missed.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224955 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu 2014-12-29 21:18:02 +00:00
parent af94b8a441
commit 23f1cd311f
1 changed files with 1 additions and 1 deletions
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lib/Target/Hexagon/HexagonInstrInfo.td
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@ -4124,7 +4124,7 @@ def : Pat<(store (i1 -1), ADDRriS11_2:$addr),
// Map from memb(Rs) = Pd -> Rt = mux(Pd, #0, #1); store Rt. // Map from memb(Rs) = Pd -> Rt = mux(Pd, #0, #1); store Rt.
def : Pat<(store (i1 PredRegs:$src1), ADDRriS11_2:$addr), def : Pat<(store (i1 PredRegs:$src1), ADDRriS11_2:$addr),
(S2_storerb_io ADDRriS11_2:$addr, 0, (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0)) )>; (S2_storerb_io AddrFI:$addr, 0, (i32 (C2_muxii (i1 PredRegs:$src1), 1, 0)) )>;
// Map Rdd = anyext(Rs) -> Rdd = A2_sxtw(Rs). // Map Rdd = anyext(Rs) -> Rdd = A2_sxtw(Rs).
// Hexagon_TODO: We can probably use combine but that will cost 2 instructions. // Hexagon_TODO: We can probably use combine but that will cost 2 instructions.