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Peephole optimization for ABS on ARM.
Patch by Ana Pazos! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141365 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -47,6 +47,11 @@ CheckVMLxHazard("check-vmlx-hazard", cl::Hidden,
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cl::desc("Check fp vmla / vmls hazard at isel time"),
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cl::init(true));
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static cl::opt<bool>
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DisableARMIntABS("disable-arm-int-abs", cl::Hidden,
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cl::desc("Enable / disable ARM integer abs transform"),
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cl::init(false));
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//===--------------------------------------------------------------------===//
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/// ARMDAGToDAGISel - ARM specific code to select ARM machine
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/// instructions for SelectionDAG operations.
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@ -252,6 +257,9 @@ private:
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ARMCC::CondCodes CCVal, SDValue CCR,
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SDValue InFlag);
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// Select special operations if node forms integer ABS pattern
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SDNode *SelectABSOp(SDNode *N);
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SDNode *SelectConcatVector(SDNode *N);
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SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
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@ -2295,6 +2303,53 @@ SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDNode *N) {
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return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
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}
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/// Target-specific DAG combining for ISD::XOR.
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/// Target-independent combining lowers SELECT_CC nodes of the form
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/// select_cc setg[ge] X, 0, X, -X
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/// select_cc setgt X, -1, X, -X
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/// select_cc setl[te] X, 0, -X, X
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/// select_cc setlt X, 1, -X, X
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/// which represent Integer ABS into:
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/// Y = sra (X, size(X)-1); xor (add (X, Y), Y)
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/// ARM instruction selection detects the latter and matches it to
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/// ARM::ABS or ARM::t2ABS machine node.
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SDNode *ARMDAGToDAGISel::SelectABSOp(SDNode *N){
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SDValue XORSrc0 = N->getOperand(0);
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SDValue XORSrc1 = N->getOperand(1);
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DebugLoc DL = N->getDebugLoc();
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EVT VT = N->getValueType(0);
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if (DisableARMIntABS)
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return NULL;
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if (XORSrc0.getOpcode() != ISD::ADD ||
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XORSrc1.getOpcode() != ISD::SRA)
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return NULL;
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SDValue ADDSrc0 = XORSrc0.getOperand(0);
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SDValue ADDSrc1 = XORSrc0.getOperand(1);
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SDValue SRASrc0 = XORSrc1.getOperand(0);
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SDValue SRASrc1 = XORSrc1.getOperand(1);
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ConstantSDNode *SRAConstant = dyn_cast<ConstantSDNode>(SRASrc1);
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EVT XType = SRASrc0.getValueType();
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unsigned Size = XType.getSizeInBits() - 1;
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if (ADDSrc1 == XORSrc1 &&
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ADDSrc0 == SRASrc0 &&
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XType.isInteger() &&
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SRAConstant != NULL &&
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Size == SRAConstant->getZExtValue()) {
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unsigned Opcode = ARM::ABS;
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if (Subtarget->isThumb2())
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Opcode = ARM::t2ABS;
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return CurDAG->SelectNodeTo(N, Opcode, VT, ADDSrc0);
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}
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return NULL;
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}
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SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) {
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// The only time a CONCAT_VECTORS operation can have legal types is when
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// two 64-bit vectors are concatenated to a 128-bit vector.
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@ -2331,6 +2386,14 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
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switch (N->getOpcode()) {
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default: break;
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case ISD::XOR: {
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// Select special operations if XOR node forms integer ABS pattern
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SDNode *ResNode = SelectABSOp(N);
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if (ResNode)
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return ResNode;
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// Other cases are autogenerated.
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break;
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}
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case ISD::Constant: {
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unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
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bool UseCP = true;
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@ -6100,6 +6100,86 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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MI->eraseFromParent(); // The pseudo instruction is gone now.
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return BB;
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}
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case ARM::ABS:
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case ARM::t2ABS: {
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// To insert an ABS instruction, we have to insert the
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// diamond control-flow pattern. The incoming instruction knows the
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// source vreg to test against 0, the destination vreg to set,
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// the condition code register to branch on, the
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// true/false values to select between, and a branch opcode to use.
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// It transforms
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// V1 = ABS V0
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// into
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// V2 = MOVS V0
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// BCC (branch to SinkBB if V0 >= 0)
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// RSBBB: V3 = RSBri V2, 0 (compute ABS if V2 < 0)
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// SinkBB: V1 = PHI(V2, V3)
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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MachineFunction::iterator BBI = BB;
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++BBI;
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MachineFunction *Fn = BB->getParent();
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MachineBasicBlock *RSBBB = Fn->CreateMachineBasicBlock(LLVM_BB);
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MachineBasicBlock *SinkBB = Fn->CreateMachineBasicBlock(LLVM_BB);
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Fn->insert(BBI, RSBBB);
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Fn->insert(BBI, SinkBB);
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unsigned int ABSSrcReg = MI->getOperand(1).getReg();
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unsigned int ABSDstReg = MI->getOperand(0).getReg();
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bool isThumb2 = Subtarget->isThumb2();
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MachineRegisterInfo &MRI = Fn->getRegInfo();
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// In Thumb mode S must not be specified if source register is the SP or
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// PC and if destination register is the SP, so restrict register class
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unsigned NewMovDstReg = MRI.createVirtualRegister(
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isThumb2 ? ARM::rGPRRegisterClass : ARM::GPRRegisterClass);
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unsigned NewRsbDstReg = MRI.createVirtualRegister(
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isThumb2 ? ARM::rGPRRegisterClass : ARM::GPRRegisterClass);
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// Transfer the remainder of BB and its successor edges to sinkMBB.
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SinkBB->splice(SinkBB->begin(), BB,
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llvm::next(MachineBasicBlock::iterator(MI)),
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BB->end());
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SinkBB->transferSuccessorsAndUpdatePHIs(BB);
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BB->addSuccessor(RSBBB);
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BB->addSuccessor(SinkBB);
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// fall through to SinkMBB
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RSBBB->addSuccessor(SinkBB);
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// insert a movs at the end of BB
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BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2MOVr : ARM::MOVr),
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NewMovDstReg)
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.addReg(ABSSrcReg, RegState::Kill)
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.addImm((unsigned)ARMCC::AL).addReg(0)
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.addReg(ARM::CPSR, RegState::Define);
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// insert a bcc with opposite CC to ARMCC::MI at the end of BB
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BuildMI(BB, dl,
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TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)).addMBB(SinkBB)
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.addImm(ARMCC::getOppositeCondition(ARMCC::MI)).addReg(ARM::CPSR);
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// insert rsbri in RSBBB
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// Note: BCC and rsbri will be converted into predicated rsbmi
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// by if-conversion pass
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BuildMI(*RSBBB, RSBBB->begin(), dl,
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TII->get(isThumb2 ? ARM::t2RSBri : ARM::RSBri), NewRsbDstReg)
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.addReg(NewMovDstReg, RegState::Kill)
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.addImm(0).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
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// insert PHI in SinkBB,
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// reuse ABSDstReg to not change uses of ABS instruction
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BuildMI(*SinkBB, SinkBB->begin(), dl,
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TII->get(ARM::PHI), ABSDstReg)
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.addReg(NewRsbDstReg).addMBB(RSBBB)
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.addReg(NewMovDstReg).addMBB(BB);
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// remove ABS instruction
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MI->eraseFromParent();
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// return last added BB
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return SinkBB;
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}
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}
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}
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@ -2848,6 +2848,9 @@ def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
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let Inst{15-12} = Rd;
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}
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def : ARMInstAlias<"movs${p} $Rd, $Rm",
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(MOVr GPR:$Rd, GPR:$Rm, pred:$p, CPSR)>;
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// A version for the smaller set of tail call registers.
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let neverHasSideEffects = 1 in
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def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
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@ -4025,6 +4028,14 @@ def ISB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
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let Inst{3-0} = opt;
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}
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// Pseudo isntruction that combines movs + predicated rsbmi
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// to implement integer ABS
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let usesCustomInserter = 1, Defs = [CPSR] in {
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def ABS : ARMPseudoInst<
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(outs GPR:$dst), (ins GPR:$src),
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8, NoItinerary, []>;
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}
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let usesCustomInserter = 1 in {
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let Defs = [CPSR] in {
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def ATOMIC_LOAD_ADD_I8 : PseudoInst<
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@ -3433,6 +3433,14 @@ def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp),
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[(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
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imm:$cp))]>,
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Requires<[IsThumb2]>;
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// Pseudo isntruction that combines movs + predicated rsbmi
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// to implement integer ABS
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let usesCustomInserter = 1, Defs = [CPSR] in {
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def t2ABS : PseudoInst<(outs rGPR:$dst), (ins rGPR:$src),
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NoItinerary, []>, Requires<[IsThumb2]>;
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}
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//===----------------------------------------------------------------------===//
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// Coprocessor load/store -- for disassembly only
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//
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@ -1,8 +1,8 @@
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; RUN: llc < %s -march=arm -mattr=+v4t | FileCheck %s
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;; Integer absolute value, should produce something as good as: ARM:
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;; add r3, r0, r0, asr #31
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;; eor r0, r3, r0, asr #31
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;; movs r0, r0
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;; rsbmi r0, r0, #0
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;; bx lr
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define i32 @test(i32 %a) {
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@ -10,7 +10,7 @@ define i32 @test(i32 %a) {
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%b = icmp sgt i32 %a, -1
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%abs = select i1 %b, i32 %a, i32 %tmp1neg
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ret i32 %abs
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; CHECK: add r1, r0, r0, asr #31
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; CHECK: eor r0, r1, r0, asr #31
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; CHECK: movs r0, r0
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; CHECK: rsbmi r0, r0, #0
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; CHECK: bx lr
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}
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@ -3,9 +3,9 @@
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;; Integer absolute value, should produce something as good as:
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;; Thumb:
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;; asr r2, r0, #31
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;; add r0, r0, r2
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;; eor r0, r2
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;; movs r0, r0
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;; bpl
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;; rsb r0, r0, #0 (with opitmization, bpl + rsb is if-converted into rsbmi)
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;; bx lr
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define i32 @test(i32 %a) {
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@ -13,5 +13,10 @@ define i32 @test(i32 %a) {
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%b = icmp sgt i32 %a, -1
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%abs = select i1 %b, i32 %a, i32 %tmp1neg
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ret i32 %abs
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; CHECK: movs r0, r0
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; CHECK: bpl
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; CHECK: rsb r0, r0, #0
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; CHECK: bx lr
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}
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