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[x86] Regenerate precise FileCheck lines for the lats batch of test
cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218954 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chandler Carruth
parent
174121596e
commit
2470f448ac
File diff suppressed because it is too large
Load Diff
@ -3,270 +3,254 @@
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; Verify that we don't emit packed vector shifts instructions if the
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; condition used by the vector select is a vector of constants.
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define <4 x float> @test1(<4 x float> %a, <4 x float> %b) {
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; CHECK-LABEL: test1:
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; CHECK: # BB#0:
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; CHECK-NEXT: andps {{.*}}(%rip), %xmm1
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; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
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; CHECK-NEXT: orps %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = select <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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; CHECK-LABEL: test1
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: ret
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define <4 x float> @test2(<4 x float> %a, <4 x float> %b) {
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; CHECK-LABEL: test2:
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; CHECK: # BB#0:
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; CHECK-NEXT: movsd %xmm0, %xmm1
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; CHECK-NEXT: movaps %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = select <4 x i1> <i1 true, i1 true, i1 false, i1 false>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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; CHECK-LABEL: test2
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: ret
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define <4 x float> @test3(<4 x float> %a, <4 x float> %b) {
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; CHECK-LABEL: test3:
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; CHECK: # BB#0:
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; CHECK-NEXT: movsd %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = select <4 x i1> <i1 false, i1 false, i1 true, i1 true>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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; CHECK-LABEL: test3
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: ret
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define <4 x float> @test4(<4 x float> %a, <4 x float> %b) {
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; CHECK-LABEL: test4:
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; CHECK: # BB#0:
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; CHECK-NEXT: movaps %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = select <4 x i1> <i1 false, i1 false, i1 false, i1 false>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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; CHECK-LABEL: test4
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: movaps %xmm1, %xmm0
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; CHECK: ret
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define <4 x float> @test5(<4 x float> %a, <4 x float> %b) {
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; CHECK-LABEL: test5:
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; CHECK: # BB#0:
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; CHECK-NEXT: retq
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%1 = select <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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; CHECK-LABEL: test5
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: ret
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define <8 x i16> @test6(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: test6:
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; CHECK: # BB#0:
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; CHECK-NEXT: movaps {{.*#+}} xmm1 = [0,65535,0,65535,0,65535,0,65535]
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; CHECK-NEXT: andps %xmm0, %xmm1
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; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
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; CHECK-NEXT: orps %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = select <8 x i1> <i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false>, <8 x i16> %a, <8 x i16> %a
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test6
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: ret
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define <8 x i16> @test7(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: test7:
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; CHECK: # BB#0:
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; CHECK-NEXT: andps {{.*}}(%rip), %xmm1
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; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
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; CHECK-NEXT: orps %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = select <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test7
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: ret
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define <8 x i16> @test8(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: test8:
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; CHECK: # BB#0:
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; CHECK-NEXT: andps {{.*}}(%rip), %xmm1
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; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
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; CHECK-NEXT: orps %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = select <8 x i1> <i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test8
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: ret
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define <8 x i16> @test9(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: test9:
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; CHECK: # BB#0:
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; CHECK-NEXT: movaps %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = select <8 x i1> <i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test9
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: movaps %xmm1, %xmm0
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; CHECK-NEXT: ret
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define <8 x i16> @test10(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: test10:
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; CHECK: # BB#0:
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; CHECK-NEXT: retq
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%1 = select <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test10
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: ret
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define <8 x i16> @test11(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: test11:
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; CHECK: # BB#0:
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; CHECK-NEXT: movaps {{.*#+}} xmm2 = <0,65535,65535,0,u,65535,65535,u>
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; CHECK-NEXT: andps %xmm2, %xmm0
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; CHECK-NEXT: andnps %xmm1, %xmm2
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; CHECK-NEXT: orps %xmm0, %xmm2
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; CHECK-NEXT: movaps %xmm2, %xmm0
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; CHECK-NEXT: retq
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%1 = select <8 x i1> <i1 false, i1 true, i1 true, i1 false, i1 undef, i1 true, i1 true, i1 undef>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test11
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: ret
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define <8 x i16> @test12(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: test12:
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; CHECK: # BB#0:
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; CHECK-NEXT: movaps %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = select <8 x i1> <i1 false, i1 false, i1 undef, i1 false, i1 false, i1 false, i1 false, i1 undef>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test12
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: ret
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define <8 x i16> @test13(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: test13:
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; CHECK: # BB#0:
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; CHECK-NEXT: movaps %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = select <8 x i1> <i1 undef, i1 undef, i1 undef, i1 undef, i1 undef, i1 undef, i1 undef, i1 undef>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test13
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK: ret
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; Fold (vselect (build_vector AllOnes), N1, N2) -> N1
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define <4 x float> @test14(<4 x float> %a, <4 x float> %b) {
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; CHECK-LABEL: test14:
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; CHECK: # BB#0:
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; CHECK-NEXT: retq
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%1 = select <4 x i1> <i1 true, i1 undef, i1 true, i1 undef>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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; CHECK-LABEL: test14
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK-NOT: pcmpeq
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; CHECK: ret
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define <8 x i16> @test15(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: test15:
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; CHECK: # BB#0:
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; CHECK-NEXT: retq
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%1 = select <8 x i1> <i1 true, i1 true, i1 true, i1 undef, i1 undef, i1 true, i1 true, i1 undef>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test15
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK-NOT: pcmpeq
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; CHECK: ret
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; Fold (vselect (build_vector AllZeros), N1, N2) -> N2
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define <4 x float> @test16(<4 x float> %a, <4 x float> %b) {
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; CHECK-LABEL: test16:
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; CHECK: # BB#0:
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; CHECK-NEXT: movaps %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = select <4 x i1> <i1 false, i1 undef, i1 false, i1 undef>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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; CHECK-LABEL: test16
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK-NOT: xorps
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; CHECK: ret
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}
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define <8 x i16> @test17(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: test17:
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; CHECK: # BB#0:
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; CHECK-NEXT: movaps %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = select <8 x i1> <i1 false, i1 false, i1 false, i1 undef, i1 undef, i1 false, i1 false, i1 undef>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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; CHECK-LABEL: test17
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK-NOT: xorps
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; CHECK: ret
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define <4 x float> @test18(<4 x float> %a, <4 x float> %b) {
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; CHECK-LABEL: test18:
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; CHECK: # BB#0:
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; CHECK-NEXT: movss %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = select <4 x i1> <i1 false, i1 true, i1 true, i1 true>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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; CHECK-LABEL: test18
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK-NOT: xorps
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; CHECK: movss
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; CHECK: ret
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define <4 x i32> @test19(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: test19:
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; CHECK: # BB#0:
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; CHECK-NEXT: movss %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = select <4 x i1> <i1 false, i1 true, i1 true, i1 true>, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %1
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}
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; CHECK-LABEL: test19
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK-NOT: xorps
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; CHECK: movss
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; CHECK: ret
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define <2 x double> @test20(<2 x double> %a, <2 x double> %b) {
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; CHECK-LABEL: test20:
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; CHECK: # BB#0:
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; CHECK-NEXT: movsd %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = select <2 x i1> <i1 false, i1 true>, <2 x double> %a, <2 x double> %b
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ret <2 x double> %1
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}
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; CHECK-LABEL: test20
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK-NOT: xorps
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; CHECK: movsd
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; CHECK: ret
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define <2 x i64> @test21(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test21:
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; CHECK: # BB#0:
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; CHECK-NEXT: movsd %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = select <2 x i1> <i1 false, i1 true>, <2 x i64> %a, <2 x i64> %b
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ret <2 x i64> %1
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}
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; CHECK-LABEL: test21
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK-NOT: xorps
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; CHECK: movsd
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; CHECK: ret
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define <4 x float> @test22(<4 x float> %a, <4 x float> %b) {
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; CHECK-LABEL: test22:
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; CHECK: # BB#0:
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; CHECK-NEXT: movss %xmm0, %xmm1
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; CHECK-NEXT: movaps %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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; CHECK-LABEL: test22
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK-NOT: xorps
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; CHECK: movss
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; CHECK: ret
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define <4 x i32> @test23(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: test23:
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; CHECK: # BB#0:
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; CHECK-NEXT: movss %xmm0, %xmm1
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; CHECK-NEXT: movaps %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %1
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}
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; CHECK-LABEL: test23
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK-NOT: xorps
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; CHECK: movss
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; CHECK: ret
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define <2 x double> @test24(<2 x double> %a, <2 x double> %b) {
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; CHECK-LABEL: test24:
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; CHECK: # BB#0:
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; CHECK-NEXT: movsd %xmm0, %xmm1
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; CHECK-NEXT: movaps %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = select <2 x i1> <i1 true, i1 false>, <2 x double> %a, <2 x double> %b
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ret <2 x double> %1
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}
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; CHECK-LABEL: test24
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK-NOT: xorps
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; CHECK: movsd
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; CHECK: ret
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define <2 x i64> @test25(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test25:
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; CHECK: # BB#0:
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; CHECK-NEXT: movsd %xmm0, %xmm1
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; CHECK-NEXT: movaps %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = select <2 x i1> <i1 true, i1 false>, <2 x i64> %a, <2 x i64> %b
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ret <2 x i64> %1
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}
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; CHECK-LABEL: test25
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; CHECK-NOT: psllw
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; CHECK-NOT: psraw
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; CHECK-NOT: xorps
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; CHECK: movsd
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; CHECK: ret
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define <4 x float> @select_of_shuffles_0(<2 x float> %a0, <2 x float> %b0, <2 x float> %a1, <2 x float> %b1) {
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; CHECK-LABEL: select_of_shuffles_0
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; CHECK-DAG: movlhps %xmm2, [[REGA:%xmm[0-9]+]]
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; CHECK-DAG: movlhps %xmm3, [[REGB:%xmm[0-9]+]]
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; CHECK: subps [[REGB]], [[REGA]]
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; CHECK-LABEL: select_of_shuffles_0:
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; CHECK: # BB#0:
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; CHECK-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
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; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm3[0]
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; CHECK-NEXT: subps %xmm1, %xmm0
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; CHECK-NEXT: retq
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%1 = shufflevector <2 x float> %a0, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
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||||
%2 = shufflevector <2 x float> %a1, <2 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1>
|
||||
%3 = select <4 x i1> <i1 false, i1 false, i1 true, i1 true>, <4 x float> %2, <4 x float> %1
|
||||
@ -277,11 +261,23 @@ define <4 x float> @select_of_shuffles_0(<2 x float> %a0, <2 x float> %b0, <2 x
|
||||
ret <4 x float> %7
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @select_illegal
|
||||
; CHECK: mov
|
||||
; CHECK: ret
|
||||
; PR20677
|
||||
define <16 x double> @select_illegal(<16 x double> %a, <16 x double> %b) {
|
||||
; CHECK-LABEL: select_illegal:
|
||||
; CHECK: # BB#0:
|
||||
; CHECK-NEXT: movaps {{[0-9]+}}(%rsp), %xmm4
|
||||
; CHECK-NEXT: movaps {{[0-9]+}}(%rsp), %xmm5
|
||||
; CHECK-NEXT: movaps {{[0-9]+}}(%rsp), %xmm6
|
||||
; CHECK-NEXT: movaps {{[0-9]+}}(%rsp), %xmm7
|
||||
; CHECK-NEXT: movaps %xmm7, 112(%rdi)
|
||||
; CHECK-NEXT: movaps %xmm6, 96(%rdi)
|
||||
; CHECK-NEXT: movaps %xmm5, 80(%rdi)
|
||||
; CHECK-NEXT: movaps %xmm4, 64(%rdi)
|
||||
; CHECK-NEXT: movaps %xmm3, 48(%rdi)
|
||||
; CHECK-NEXT: movaps %xmm2, 32(%rdi)
|
||||
; CHECK-NEXT: movaps %xmm1, 16(%rdi)
|
||||
; CHECK-NEXT: movaps %xmm0, (%rdi)
|
||||
; CHECK-NEXT: retq
|
||||
%sel = select <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <16 x double> %a, <16 x double> %b
|
||||
ret <16 x double> %sel
|
||||
}
|
||||
|
||||
@ -2,42 +2,53 @@
|
||||
|
||||
; widening shuffle v3float and then a add
|
||||
define void @shuf(<3 x float>* %dst.addr, <3 x float> %src1,<3 x float> %src2) nounwind {
|
||||
entry:
|
||||
; CHECK-LABEL: shuf:
|
||||
; CHECK: extractps
|
||||
; CHECK: extractps
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
|
||||
; CHECK-NEXT: addps %xmm1, %xmm0
|
||||
; CHECK-NEXT: extractps $2, %xmm0, 8(%eax)
|
||||
; CHECK-NEXT: extractps $1, %xmm0, 4(%eax)
|
||||
; CHECK-NEXT: movss %xmm0, (%eax)
|
||||
; CHECK-NEXT: retl
|
||||
entry:
|
||||
%x = shufflevector <3 x float> %src1, <3 x float> %src2, <3 x i32> < i32 0, i32 1, i32 2>
|
||||
%val = fadd <3 x float> %x, %src2
|
||||
store <3 x float> %val, <3 x float>* %dst.addr
|
||||
ret void
|
||||
; CHECK: ret
|
||||
}
|
||||
|
||||
|
||||
; widening shuffle v3float with a different mask and then a add
|
||||
define void @shuf2(<3 x float>* %dst.addr, <3 x float> %src1,<3 x float> %src2) nounwind {
|
||||
entry:
|
||||
; CHECK-LABEL: shuf2:
|
||||
; CHECK: extractps
|
||||
; CHECK: extractps
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
|
||||
; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]
|
||||
; CHECK-NEXT: addps %xmm1, %xmm0
|
||||
; CHECK-NEXT: extractps $2, %xmm0, 8(%eax)
|
||||
; CHECK-NEXT: extractps $1, %xmm0, 4(%eax)
|
||||
; CHECK-NEXT: movss %xmm0, (%eax)
|
||||
; CHECK-NEXT: retl
|
||||
entry:
|
||||
%x = shufflevector <3 x float> %src1, <3 x float> %src2, <3 x i32> < i32 0, i32 4, i32 2>
|
||||
%val = fadd <3 x float> %x, %src2
|
||||
store <3 x float> %val, <3 x float>* %dst.addr
|
||||
ret void
|
||||
; CHECK: ret
|
||||
}
|
||||
|
||||
; Example of when widening a v3float operation causes the DAG to replace a node
|
||||
; with the operation that we are currently widening, i.e. when replacing
|
||||
; opA with opB, the DAG will produce new operations with opA.
|
||||
define void @shuf3(<4 x float> %tmp10, <4 x float> %vecinit15, <4 x float>* %dst) nounwind {
|
||||
entry:
|
||||
; CHECK-LABEL: shuf3:
|
||||
; CHECK-NOT: movlhps
|
||||
; CHECK-NOT: shufps
|
||||
; CHECK: pshufd
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
|
||||
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,0,0,0]
|
||||
; CHECK-NEXT: movdqa %xmm0, (%eax)
|
||||
; CHECK-NEXT: retl
|
||||
entry:
|
||||
%shuffle.i.i.i12 = shufflevector <4 x float> %tmp10, <4 x float> %vecinit15, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
|
||||
%tmp25.i.i = shufflevector <4 x float> %shuffle.i.i.i12, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
|
||||
%tmp25.i.i = shufflevector <4 x float> %shuffle.i.i.i12, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
|
||||
%tmp1.i.i = shufflevector <3 x float> %tmp25.i.i, <3 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
||||
%tmp3.i13 = shufflevector <4 x float> %tmp1.i.i, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2> ; <<3 x float>>
|
||||
%tmp6.i14 = shufflevector <3 x float> %tmp3.i13, <3 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
||||
@ -45,27 +56,34 @@ entry:
|
||||
%tmp2.i18 = shufflevector <3 x float> %tmp97.i, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
|
||||
%t5 = bitcast <4 x float> %tmp2.i18 to <4 x i32>
|
||||
%shr.i.i19 = lshr <4 x i32> %t5, <i32 19, i32 19, i32 19, i32 19>
|
||||
%and.i.i20 = and <4 x i32> %shr.i.i19, <i32 4080, i32 4080, i32 4080, i32 4080>
|
||||
%and.i.i20 = and <4 x i32> %shr.i.i19, <i32 4080, i32 4080, i32 4080, i32 4080>
|
||||
%shuffle.i.i.i21 = shufflevector <4 x float> %tmp2.i18, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 2, i32 3>
|
||||
store <4 x float> %shuffle.i.i.i21, <4 x float>* %dst
|
||||
ret void
|
||||
; CHECK: ret
|
||||
}
|
||||
|
||||
; PR10421: make sure we correctly handle extreme widening with CONCAT_VECTORS
|
||||
define <8 x i8> @shuf4(<4 x i8> %a, <4 x i8> %b) nounwind readnone {
|
||||
; CHECK-LABEL: shuf4:
|
||||
; CHECK-NOT: punpckldq
|
||||
; CHECK: # BB#0:
|
||||
; CHECK-NEXT: pshufb {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0],zero,xmm1[4],zero,xmm1[8],zero,xmm1[12],zero
|
||||
; CHECK-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0],zero,xmm0[4],zero,xmm0[8],zero,xmm0[12],zero,zero,zero,zero,zero,zero,zero,zero,zero
|
||||
; CHECK-NEXT: por %xmm1, %xmm0
|
||||
; CHECK-NEXT: retl
|
||||
%vshuf = shufflevector <4 x i8> %a, <4 x i8> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
||||
ret <8 x i8> %vshuf
|
||||
; CHECK: ret
|
||||
}
|
||||
|
||||
; PR11389: another CONCAT_VECTORS case
|
||||
define void @shuf5(<8 x i8>* %p) nounwind {
|
||||
; CHECK-LABEL: shuf5:
|
||||
; CHECK: # BB#0:
|
||||
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
|
||||
; CHECK-NEXT: movdqa {{.*#+}} xmm0 = <4,33,u,u,u,u,u,u>
|
||||
; CHECK-NEXT: pshufb {{.*#+}} xmm0 = xmm0[2,2,0,0,8,10,12,14],zero,zero,zero,zero,zero,zero,zero,zero
|
||||
; CHECK-NEXT: movlpd %xmm0, (%eax)
|
||||
; CHECK-NEXT: retl
|
||||
%v = shufflevector <2 x i8> <i8 4, i8 33>, <2 x i8> undef, <8 x i32> <i32 1, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
|
||||
store <8 x i8> %v, <8 x i8>* %p, align 8
|
||||
ret void
|
||||
; CHECK: ret
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user