MIRParser/MIRPrinter: Compute HasInlineAsm instead of printing/parsing it

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279680 91177308-0d34-0410-b5e6-96231b3b80d8
2025-01-09 05:31:37 +00:00 · 2016-08-24 22:34:06 +00:00 · 2016-08-24 22:34:06 +00:00 · 249a3152c0
commit 249a3152c0
parent 6928bc96df
22 changed files with 13 additions and 45 deletions
--- a/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/lib/CodeGen/MIRParser/MIRParser.cpp
@ -281,14 +281,6 @@ void MIRParserImpl::createDummyFunction(StringRef Name, Module &M) {
  new UnreachableInst(Context, BB);
 }

-static bool hasPHI(const MachineFunction &MF) {
-  for (const MachineBasicBlock &MBB : MF)
-    for (const MachineInstr &MI : MBB)
-      if (MI.isPHI())
-        return true;
-  return false;
-}
-
 static bool isSSA(const MachineFunction &MF) {
  const MachineRegisterInfo &MRI = MF.getRegInfo();
  for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
@ -301,8 +293,20 @@ static bool isSSA(const MachineFunction &MF) {

 void MIRParserImpl::computeFunctionProperties(MachineFunction &MF) {
  MachineFunctionProperties &Properties = MF.getProperties();
-  if (!hasPHI(MF))
+
+  bool HasPHI = false;
+  bool HasInlineAsm = false;
+  for (const MachineBasicBlock &MBB : MF) {
+    for (const MachineInstr &MI : MBB) {
+      if (MI.isPHI())
+        HasPHI = true;
+      if (MI.isInlineAsm())
+        HasInlineAsm = true;
+    }
+  }
+  if (!HasPHI)
    Properties.set(MachineFunctionProperties::Property::NoPHIs);
+  MF.setHasInlineAsm(HasInlineAsm);

  if (isSSA(MF))
    Properties.set(MachineFunctionProperties::Property::IsSSA);
@ -320,7 +324,6 @@ bool MIRParserImpl::initializeMachineFunction(MachineFunction &MF) {
  if (YamlMF.Alignment)
    MF.setAlignment(YamlMF.Alignment);
  MF.setExposesReturnsTwice(YamlMF.ExposesReturnsTwice);
-  MF.setHasInlineAsm(YamlMF.HasInlineAsm);
  if (YamlMF.AllVRegsAllocated)
    MF.getProperties().set(MachineFunctionProperties::Property::AllVRegsAllocated);

--- a/lib/CodeGen/MIRPrinter.cpp
+++ b/lib/CodeGen/MIRPrinter.cpp
@ -174,7 +174,6 @@ void MIRPrinter::print(const MachineFunction &MF) {
  YamlMF.Name = MF.getName();
  YamlMF.Alignment = MF.getAlignment();
  YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
-  YamlMF.HasInlineAsm = MF.hasInlineAsm();
  YamlMF.AllVRegsAllocated = MF.getProperties().hasProperty(
      MachineFunctionProperties::Property::AllVRegsAllocated);

--- a/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir
+++ b/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir
@ -28,7 +28,6 @@
 name:            promote-load-from-store
 alignment:       2
 exposesReturnsTwice: false
-hasInlineAsm:    false
 allVRegsAllocated: true
 tracksRegLiveness: false
 liveins:         
@ -84,7 +83,6 @@ body:             |
 name:            store-pair
 alignment:       2
 exposesReturnsTwice: false
-hasInlineAsm:    false
 allVRegsAllocated: true
 tracksRegLiveness: false
 liveins:         
--- a/test/CodeGen/AArch64/movimm-wzr.mir
+++ b/test/CodeGen/AArch64/movimm-wzr.mir
@ -15,7 +15,6 @@
 name:            test_mov_0
 alignment:       2
 exposesReturnsTwice: false
-hasInlineAsm:    false
 allVRegsAllocated: true
 tracksRegLiveness: false
 frameInfo:
--- a/test/CodeGen/ARM/ARMLoadStoreDBG.mir
+++ b/test/CodeGen/ARM/ARMLoadStoreDBG.mir
@ -79,7 +79,6 @@
 name:            f
 alignment:       1
 exposesReturnsTwice: false
-hasInlineAsm:    false
 allVRegsAllocated: true
 tracksRegLiveness: true
 liveins:
--- a/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir
+++ b/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir
@ -33,7 +33,6 @@
 name:            test_tlsdesc_callseq_length
 alignment:       2
 exposesReturnsTwice: false
-hasInlineAsm:    false
 allVRegsAllocated: true
 tracksRegLiveness: false
 liveins:
--- a/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir
+++ b/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir
@ -90,7 +90,6 @@
 name:            f
 alignment:       1
 exposesReturnsTwice: false
-hasInlineAsm:    false
 allVRegsAllocated: true
 tracksRegLiveness: true
 liveins:
--- a/test/CodeGen/MIR/Generic/machine-function.mir
+++ b/test/CodeGen/MIR/Generic/machine-function.mir
@ -24,7 +24,6 @@
 # CHECK: name: foo
 # CHECK-NEXT: alignment:
 # CHECK-NEXT: exposesReturnsTwice: false
-# CHECK-NEXT: hasInlineAsm: false
 # CHECK: ...
 name:            foo
 body: |
@ -34,7 +33,6 @@ body: |
 # CHECK: name: bar
 # CHECK-NEXT: alignment:
 # CHECK-NEXT: exposesReturnsTwice: false
-# CHECK-NEXT: hasInlineAsm: false
 # CHECK: ...
 name:            bar
 body: |
@ -44,7 +42,6 @@ body: |
 # CHECK: name: func
 # CHECK-NEXT: alignment: 8
 # CHECK-NEXT: exposesReturnsTwice: false
-# CHECK-NEXT: hasInlineAsm: false
 # CHECK: ...
 name:            func
 alignment:       8
@ -55,12 +52,10 @@ body: |
 # CHECK: name: func2
 # CHECK-NEXT: alignment: 16
 # CHECK-NEXT: exposesReturnsTwice: true
-# CHECK-NEXT: hasInlineAsm: true
 # CHECK: ...
 name:            func2
 alignment:       16
 exposesReturnsTwice: true
-hasInlineAsm:    true
 body: |
  bb.0:
 ...
--- a/test/CodeGen/MIR/Lanai/peephole-compare.mir
+++ b/test/CodeGen/MIR/Lanai/peephole-compare.mir
@ -175,7 +175,6 @@
 name:            test0a
 alignment:       2
 exposesReturnsTwice: false
-hasInlineAsm:    false
 allVRegsAllocated: false
 tracksRegLiveness: true
 registers:       
@ -221,7 +220,6 @@ body:             |
 name:            test0b
 alignment:       2
 exposesReturnsTwice: false
-hasInlineAsm:    false
 allVRegsAllocated: false
 tracksRegLiveness: true
 registers:       
@ -265,7 +263,6 @@ body:             |
 name:            test1a
 alignment:       2
 exposesReturnsTwice: false
-hasInlineAsm:    false
 allVRegsAllocated: false
 tracksRegLiveness: true
 registers:       
@ -313,7 +310,6 @@ body:             |
 name:            test1b
 alignment:       2
 exposesReturnsTwice: false
-hasInlineAsm:    false
 allVRegsAllocated: false
 tracksRegLiveness: true
 registers:       
@ -361,7 +357,6 @@ body:             |
 name:            test2a
 alignment:       2
 exposesReturnsTwice: false
-hasInlineAsm:    false
 allVRegsAllocated: false
 tracksRegLiveness: true
 registers:       
@ -409,7 +404,6 @@ body:             |
 name:            test2b
 alignment:       2
 exposesReturnsTwice: false
-hasInlineAsm:    false
 allVRegsAllocated: false
 tracksRegLiveness: true
 registers:       
@ -457,7 +451,6 @@ body:             |
 name:            test3
 alignment:       2
 exposesReturnsTwice: false
-hasInlineAsm:    false
 allVRegsAllocated: false
 tracksRegLiveness: true
 registers:       
@ -505,7 +498,6 @@ body:             |
 name:            test4
 alignment:       2
 exposesReturnsTwice: false
-hasInlineAsm:    false
 allVRegsAllocated: false
 tracksRegLiveness: true
 registers:       
@ -617,7 +609,6 @@ body:             |
 name:            testBB
 alignment:       2
 exposesReturnsTwice: false
-hasInlineAsm:    false
 allVRegsAllocated: false
 tracksRegLiveness: true
 registers:       
--- a/test/CodeGen/MIR/X86/def-register-already-tied-error.mir
+++ b/test/CodeGen/MIR/X86/def-register-already-tied-error.mir
@ -10,7 +10,6 @@
 ...
 ---
 name:            test
-hasInlineAsm:    true
 tracksRegLiveness: true
 liveins:
  - { reg: '%rdi' }
--- a/test/CodeGen/MIR/X86/early-clobber-register-flag.mir
+++ b/test/CodeGen/MIR/X86/early-clobber-register-flag.mir
@ -19,7 +19,6 @@
 ...
 ---
 name:            test
-hasInlineAsm:    true
 tracksRegLiveness: true
 liveins:
  - { reg: '%edi' }
--- a/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir
+++ b/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir
@ -10,7 +10,6 @@
 ...
 ---
 name:            test
-hasInlineAsm:    true
 tracksRegLiveness: true
 liveins:
  - { reg: '%rdi' }
--- a/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir
+++ b/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir
@ -10,7 +10,6 @@
 ...
 ---
 name:            test
-hasInlineAsm:    true
 tracksRegLiveness: true
 liveins:
  - { reg: '%rdi' }
--- a/test/CodeGen/MIR/X86/inline-asm-registers.mir
+++ b/test/CodeGen/MIR/X86/inline-asm-registers.mir
@ -19,7 +19,6 @@
 ...
 ---
 name:            test
-hasInlineAsm:    true
 tracksRegLiveness: true
 liveins:
  - { reg: '%rdi' }
@ -36,7 +35,6 @@ body: |
 ...
 ---
 name:            test2
-hasInlineAsm:    true
 tracksRegLiveness: true
 liveins:
  - { reg: '%rdi' }
--- a/test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir
+++ b/test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir
@ -10,7 +10,6 @@
 ...
 ---
 name:            test
-hasInlineAsm:    true
 tracksRegLiveness: true
 liveins:
  - { reg: '%rdi' }
--- a/test/CodeGen/MIR/X86/tied-def-operand-invalid.mir
+++ b/test/CodeGen/MIR/X86/tied-def-operand-invalid.mir
@ -10,7 +10,6 @@
 ...
 ---
 name:            test
-hasInlineAsm:    true
 tracksRegLiveness: true
 liveins:
  - { reg: '%rdi' }
--- a/test/CodeGen/PowerPC/aantidep-def-ec.mir
+++ b/test/CodeGen/PowerPC/aantidep-def-ec.mir
@ -44,7 +44,6 @@
 name:            mm_update_next_owner
 alignment:       4
 exposesReturnsTwice: false
-hasInlineAsm:    true
 allVRegsAllocated: true
 tracksRegLiveness: true
 liveins:         
--- a/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir
+++ b/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir
@ -26,7 +26,6 @@
 name:            test1
 alignment:       4
 exposesReturnsTwice: false
-hasInlineAsm:    false
 allVRegsAllocated: true
 tracksRegLiveness: true
 frameInfo:       
--- a/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir
+++ b/test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir
@ -39,7 +39,6 @@
 name:            main
 alignment:       2
 exposesReturnsTwice: false
-hasInlineAsm:    false
 tracksRegLiveness: true
 registers:       
  - { id: 0, class: g8rc_and_g8rc_nox0 }
--- a/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir
+++ b/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir
@ -32,7 +32,6 @@
 name:            fn1
 alignment:       2
 exposesReturnsTwice: false
-hasInlineAsm:    false
 allVRegsAllocated: false
 tracksRegLiveness: true
 registers:
--- a/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir
+++ b/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir
@ -157,7 +157,6 @@
 name:            add
 alignment:       4
 exposesReturnsTwice: false
-hasInlineAsm:    false
 allVRegsAllocated: true
 tracksRegLiveness: true
 liveins:         
--- a/test/DebugInfo/MIR/X86/live-debug-values.mir
+++ b/test/DebugInfo/MIR/X86/live-debug-values.mir
@ -159,7 +159,6 @@
 name:            main
 alignment:       4
 exposesReturnsTwice: false
-hasInlineAsm:    false
 allVRegsAllocated: true
 tracksRegLiveness: true
 liveins: