diff --git a/lib/Target/Hexagon/CMakeLists.txt b/lib/Target/Hexagon/CMakeLists.txt index fbce4bfea81..2f3dd3326fc 100644 --- a/lib/Target/Hexagon/CMakeLists.txt +++ b/lib/Target/Hexagon/CMakeLists.txt @@ -66,4 +66,3 @@ add_subdirectory(AsmParser) add_subdirectory(TargetInfo) add_subdirectory(MCTargetDesc) add_subdirectory(Disassembler) - diff --git a/lib/Target/Hexagon/Hexagon.td b/lib/Target/Hexagon/Hexagon.td index 1566f27a3a4..25388ccf590 100644 --- a/lib/Target/Hexagon/Hexagon.td +++ b/lib/Target/Hexagon/Hexagon.td @@ -241,7 +241,6 @@ def getRealHWInstr : InstrMapping { //===----------------------------------------------------------------------===// include "HexagonSchedule.td" include "HexagonRegisterInfo.td" -include "HexagonCallingConv.td" include "HexagonOperands.td" include "HexagonDepOperands.td" include "HexagonDepITypes.td" diff --git a/lib/Target/Hexagon/HexagonCallingConv.td b/lib/Target/Hexagon/HexagonCallingConv.td deleted file mode 100644 index e61b2a7a58a..00000000000 --- a/lib/Target/Hexagon/HexagonCallingConv.td +++ /dev/null @@ -1,35 +0,0 @@ -//===- HexagonCallingConv.td - Calling Conventions Hexagon -*- tablegen -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This describes the calling conventions for the Hexagon architectures. -// -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// Return Value Calling Conventions -//===----------------------------------------------------------------------===// - -// Hexagon 32-bit C return-value convention. -def RetCC_Hexagon32 : CallingConv<[ - CCIfType<[i32, f32], CCAssignToReg<[R0, R1, R2, R3, R4, R5]>>, - CCIfType<[i64, f64], CCAssignToReg<[D0, D1, D2]>>, - - // Alternatively, they are assigned to the stack in 4-byte aligned units. - CCAssignToStack<4, 4> -]>; - -// Hexagon 32-bit C Calling convention. -def CC_Hexagon32 : CallingConv<[ - // All arguments get passed in integer registers if there is space. - CCIfType<[f32, i32, i16, i8], CCAssignToReg<[R0, R1, R2, R3, R4, R5]>>, - CCIfType<[f64, i64], CCAssignToReg<[D0, D1, D2]>>, - - // Alternatively, they are assigned to the stack in 4-byte aligned units. - CCAssignToStack<4, 4> -]>; diff --git a/lib/Target/Hexagon/HexagonInstrAlias.td b/lib/Target/Hexagon/HexagonInstrAlias.td deleted file mode 100644 index b1bcbdef11f..00000000000 --- a/lib/Target/Hexagon/HexagonInstrAlias.td +++ /dev/null @@ -1,654 +0,0 @@ -//==- HexagonInstrAlias.td - Hexagon Instruction Aliases ---*- tablegen -*--==// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// Hexagon Instruction Mappings -//===----------------------------------------------------------------------===// - - -def : InstAlias<"memb({GP}+#$addr) = $Nt.new", - (S2_storerbnewgp u16_0Imm:$addr, IntRegs:$Nt)>; -def : InstAlias<"memh({GP}+#$addr) = $Nt.new", - (S2_storerhnewgp u16_1Imm:$addr, IntRegs:$Nt)>; -def : InstAlias<"memw({GP}+#$addr) = $Nt.new", - (S2_storerinewgp u16_2Imm:$addr, IntRegs:$Nt)>; -def : InstAlias<"memb({GP}+#$addr) = $Nt", - (S2_storerbgp u16_0Imm:$addr, IntRegs:$Nt)>; -def : InstAlias<"memh({GP}+#$addr) = $Nt", - (S2_storerhgp u16_1Imm:$addr, IntRegs:$Nt)>; -def : InstAlias<"memh({GP}+#$addr) = $Nt.h", - (S2_storerfgp u16_1Imm:$addr, IntRegs:$Nt)>; -def : InstAlias<"memw({GP}+#$addr) = $Nt", - (S2_storerigp u16_2Imm:$addr, IntRegs:$Nt)>; -def : InstAlias<"memd({GP}+#$addr) = $Nt", - (S2_storerdgp u16_3Imm:$addr, DoubleRegs:$Nt)>; - -def : InstAlias<"$Nt = memb({GP}+#$addr)", - (L2_loadrbgp IntRegs:$Nt, u16_0Imm:$addr)>; -def : InstAlias<"$Nt = memub({GP}+#$addr)", - (L2_loadrubgp IntRegs:$Nt, u16_0Imm:$addr)>; -def : InstAlias<"$Nt = memh({GP}+#$addr)", - (L2_loadrhgp IntRegs:$Nt, u16_1Imm:$addr)>; -def : InstAlias<"$Nt = memuh({GP}+#$addr)", - (L2_loadruhgp IntRegs:$Nt, u16_1Imm:$addr)>; -def : InstAlias<"$Nt = memw({GP}+#$addr)", - (L2_loadrigp IntRegs:$Nt, u16_2Imm:$addr)>; -def : InstAlias<"$Nt = memd({GP}+#$addr)", - (L2_loadrdgp DoubleRegs:$Nt, u16_3Imm:$addr)>; - -// Alias of: memXX($Rs+#XX) = $Rt to memXX($Rs) = $Rt -def : InstAlias<"memb($Rs) = $Rt", - (S2_storerb_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"memh($Rs) = $Rt", - (S2_storerh_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"memh($Rs) = $Rt.h", - (S2_storerf_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"memw($Rs) = $Rt", - (S2_storeri_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"memb($Rs) = $Rt.new", - (S2_storerbnew_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"memh($Rs) = $Rt.new", - (S2_storerhnew_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"memw($Rs) = $Rt.new", - (S2_storerinew_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"memb($Rs) = #$S8", - (S4_storeirb_io IntRegs:$Rs, 0, s8_0Ext:$S8), 0>; - -def : InstAlias<"memh($Rs) = #$S8", - (S4_storeirh_io IntRegs:$Rs, 0, s8_0Ext:$S8), 0>; - -def : InstAlias<"memw($Rs) = #$S8", - (S4_storeiri_io IntRegs:$Rs, 0, s8_0Ext:$S8), 0>; - -def : InstAlias<"memd($Rs) = $Rtt", - (S2_storerd_io IntRegs:$Rs, 0, DoubleRegs:$Rtt), 0>; - -def : InstAlias<"memb($Rs) = setbit(#$U5)", - (L4_ior_memopb_io IntRegs:$Rs, 0, u5_0Imm:$U5), 0>; - -def : InstAlias<"memh($Rs) = setbit(#$U5)", - (L4_ior_memoph_io IntRegs:$Rs, 0, u5_0Imm:$U5), 0>; - -def : InstAlias<"memw($Rs) = setbit(#$U5)", - (L4_ior_memopw_io IntRegs:$Rs, 0, u5_0Imm:$U5), 0>; - -def : InstAlias<"memb($Rs) = clrbit(#$U5)", - (L4_iand_memopb_io IntRegs:$Rs, 0, u5_0Imm:$U5), 0>; - -def : InstAlias<"memh($Rs) = clrbit(#$U5)", - (L4_iand_memoph_io IntRegs:$Rs, 0, u5_0Imm:$U5), 0>; - -def : InstAlias<"memw($Rs) = clrbit(#$U5)", - (L4_iand_memopw_io IntRegs:$Rs, 0, u5_0Imm:$U5), 0>; - -// Alias of: $Rd = memXX($Rs+#XX) to $Rd = memXX($Rs) -def : InstAlias<"$Rd = memb($Rs)", - (L2_loadrb_io IntRegs:$Rd, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"$Rd = memub($Rs)", - (L2_loadrub_io IntRegs:$Rd, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"$Rd = memh($Rs)", - (L2_loadrh_io IntRegs:$Rd, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"$Rd = memuh($Rs)", - (L2_loadruh_io IntRegs:$Rd, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"$Rd = memw($Rs)", - (L2_loadri_io IntRegs:$Rd, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"$Rdd = memd($Rs)", - (L2_loadrd_io DoubleRegs:$Rdd, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"$Rd = memubh($Rs)", - (L2_loadbzw2_io IntRegs:$Rd, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"$Rdd = memubh($Rs)", - (L2_loadbzw4_io DoubleRegs:$Rdd, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"$Rd = membh($Rs)", - (L2_loadbsw2_io IntRegs:$Rd, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"$Rdd = membh($Rs)", - (L2_loadbsw4_io DoubleRegs:$Rdd, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"$Rdd = memb_fifo($Rs)", - (L2_loadalignb_io DoubleRegs:$Rdd, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"$Rdd = memh_fifo($Rs)", - (L2_loadalignh_io DoubleRegs:$Rdd, IntRegs:$Rs, 0), 0>; - -// Alias of: if ($Pt) $Rd = memXX($Rs + #$u6_X) -// to: if ($Pt) $Rd = memXX($Rs) -def : InstAlias<"if ($Pt) $Rd = memb($Rs)", - (L2_ploadrbt_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"if ($Pt) $Rd = memub($Rs)", - (L2_ploadrubt_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"if ($Pt) $Rd = memh($Rs)", - (L2_ploadrht_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"if ($Pt) $Rd = memuh($Rs)", - (L2_ploadruht_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"if ($Pt) $Rd = memw($Rs)", - (L2_ploadrit_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"if ($Pt) $Rdd = memd($Rs)", - (L2_ploadrdt_io DoubleRegs:$Rdd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -// Alias of: if ($Pt) memXX($Rs + #$u6_X) = $Rt -// to: if ($Pt) memXX($Rs) = $Rt -def : InstAlias<"if ($Pt) memb($Rs) = $Rt", - (S2_pstorerbt_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if ($Pt) memh($Rs) = $Rt", - (S2_pstorerht_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if ($Pt) memh($Rs) = $Rt.h", - (S2_pstorerft_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if ($Pt) memw($Rs) = $Rt", - (S2_pstorerit_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if ($Pt) memd($Rs) = $Rtt", - (S2_pstorerdt_io PredRegs:$Pt, IntRegs:$Rs, 0, DoubleRegs:$Rtt), 0>; - -def : InstAlias<"if ($Pt) memb($Rs) = $Rt.new", - (S2_pstorerbnewt_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if ($Pt) memh($Rs) = $Rt.new", - (S2_pstorerhnewt_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if ($Pt) memw($Rs) = $Rt.new", - (S2_pstorerinewt_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if ($Pt.new) memb($Rs) = $Rt.new", - (S4_pstorerbnewtnew_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if ($Pt.new) memh($Rs) = $Rt.new", - (S4_pstorerhnewtnew_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if ($Pt.new) memw($Rs) = $Rt.new", - (S4_pstorerinewtnew_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - - -// Alias of: if (!$Pt) $Rd = memXX($Rs + #$u6_X) -// to: if (!$Pt) $Rd = memXX($Rs) -def : InstAlias<"if (!$Pt) $Rd = memb($Rs)", - (L2_ploadrbf_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"if (!$Pt) $Rd = memub($Rs)", - (L2_ploadrubf_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"if (!$Pt) $Rd = memh($Rs)", - (L2_ploadrhf_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"if (!$Pt) $Rd = memuh($Rs)", - (L2_ploadruhf_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"if (!$Pt) $Rd = memw($Rs)", - (L2_ploadrif_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"if (!$Pt) $Rdd = memd($Rs)", - (L2_ploadrdf_io DoubleRegs:$Rdd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -// Alias of: if (!$Pt) memXX($Rs + #$u6_X) = $Rt -// to: if (!$Pt) memXX($Rs) = $Rt -def : InstAlias<"if (!$Pt) memb($Rs) = $Rt", - (S2_pstorerbf_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if (!$Pt) memh($Rs) = $Rt", - (S2_pstorerhf_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if (!$Pt) memh($Rs) = $Rt.h", - (S2_pstorerff_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if (!$Pt) memw($Rs) = $Rt", - (S2_pstorerif_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if (!$Pt) memd($Rs) = $Rtt", - (S2_pstorerdf_io PredRegs:$Pt, IntRegs:$Rs, 0, DoubleRegs:$Rtt), 0>; - -def : InstAlias<"if (!$Pt) memb($Rs) = $Rt.new", - (S2_pstorerbnewf_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if (!$Pt) memh($Rs) = $Rt.new", - (S2_pstorerhnewf_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if (!$Pt) memw($Rs) = $Rt.new", - (S2_pstorerinewf_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if (!$Pt.new) memb($Rs) = $Rt.new", - (S4_pstorerbnewfnew_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if (!$Pt.new) memh($Rs) = $Rt.new", - (S4_pstorerhnewfnew_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if (!$Pt.new) memw($Rs) = $Rt.new", - (S4_pstorerinewfnew_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if ($Pt) memb($Rs) = #$S6", - (S4_storeirbt_io PredRegs:$Pt, IntRegs:$Rs, 0, s6_0Ext:$S6), 0>; - -def : InstAlias<"if ($Pt) memh($Rs) = #$S6", - (S4_storeirht_io PredRegs:$Pt, IntRegs:$Rs, 0, s6_0Ext:$S6), 0>; - -def : InstAlias<"if ($Pt) memw($Rs) = #$S6", - (S4_storeirit_io PredRegs:$Pt, IntRegs:$Rs, 0, s6_0Ext:$S6), 0>; - -def : InstAlias<"if ($Pt.new) memb($Rs) = #$S6", - (S4_storeirbtnew_io PredRegs:$Pt, IntRegs:$Rs, 0, s6_0Ext:$S6), 0>; - -def : InstAlias<"if ($Pt.new) memh($Rs) = #$S6", - (S4_storeirhtnew_io PredRegs:$Pt, IntRegs:$Rs, 0, s6_0Ext:$S6), 0>; - -def : InstAlias<"if ($Pt.new) memw($Rs) = #$S6", - (S4_storeiritnew_io PredRegs:$Pt, IntRegs:$Rs, 0, s6_0Ext:$S6), 0>; - -def : InstAlias<"if (!$Pt) memb($Rs) = #$S6", - (S4_storeirbf_io PredRegs:$Pt, IntRegs:$Rs, 0, s6_0Ext:$S6), 0>; - -def : InstAlias<"if (!$Pt) memh($Rs) = #$S6", - (S4_storeirhf_io PredRegs:$Pt, IntRegs:$Rs, 0, s6_0Ext:$S6), 0>; - -def : InstAlias<"if (!$Pt) memw($Rs) = #$S6", - (S4_storeirif_io PredRegs:$Pt, IntRegs:$Rs, 0, s6_0Ext:$S6), 0>; - -def : InstAlias<"if (!$Pt.new) memb($Rs) = #$S6", - (S4_storeirbfnew_io PredRegs:$Pt, IntRegs:$Rs, 0, s6_0Ext:$S6), 0>; - -def : InstAlias<"if (!$Pt.new) memh($Rs) = #$S6", - (S4_storeirhfnew_io PredRegs:$Pt, IntRegs:$Rs, 0, s6_0Ext:$S6), 0>; - -def : InstAlias<"if (!$Pt.new) memw($Rs) = #$S6", - (S4_storeirifnew_io PredRegs:$Pt, IntRegs:$Rs, 0, s6_0Ext:$S6), 0>; - -// Alias of: memXX($Rs + $u6_X) |= $Rt, also &=, +=, -= -// to: memXX($Rs) |= $Rt -def : InstAlias<"memb($Rs) &= $Rt", - (L4_and_memopb_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>, - Requires<[UseMEMOP]>; - -def : InstAlias<"memb($Rs) |= $Rt", - (L4_or_memopb_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>, - Requires<[UseMEMOP]>; - -def : InstAlias<"memb($Rs) += $Rt", - (L4_add_memopb_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>, - Requires<[UseMEMOP]>; - -def : InstAlias<"memb($Rs) -= $Rt", - (L4_sub_memopb_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>, - Requires<[UseMEMOP]>; - -def : InstAlias<"memb($Rs) += #$U5", - (L4_iadd_memopb_io IntRegs:$Rs, 0, u5_0Imm:$U5), 0>, - Requires<[UseMEMOP]>; - -def : InstAlias<"memb($Rs) -= #$U5", - (L4_isub_memopb_io IntRegs:$Rs, 0, u5_0Imm:$U5), 0>, - Requires<[UseMEMOP]>; - -def : InstAlias<"memh($Rs) &= $Rt", - (L4_and_memoph_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>, - Requires<[UseMEMOP]>; - -def : InstAlias<"memh($Rs) |= $Rt", - (L4_or_memoph_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>, - Requires<[UseMEMOP]>; - -def : InstAlias<"memh($Rs) += $Rt", - (L4_add_memoph_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>, - Requires<[UseMEMOP]>; - -def : InstAlias<"memh($Rs) -= $Rt", - (L4_sub_memoph_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>, - Requires<[UseMEMOP]>; - -def : InstAlias<"memh($Rs) += #$U5", - (L4_iadd_memoph_io IntRegs:$Rs, 0, u5_0Imm:$U5), 0>, - Requires<[UseMEMOP]>; - -def : InstAlias<"memh($Rs) -= #$U5", - (L4_isub_memoph_io IntRegs:$Rs, 0, u5_0Imm:$U5), 0>, - Requires<[UseMEMOP]>; - -def : InstAlias<"memw($Rs) &= $Rt", - (L4_and_memopw_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>, - Requires<[UseMEMOP]>; - -def : InstAlias<"memw($Rs) |= $Rt", - (L4_or_memopw_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>, - Requires<[UseMEMOP]>; - -def : InstAlias<"memw($Rs) += $Rt", - (L4_add_memopw_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>, - Requires<[UseMEMOP]>; - -def : InstAlias<"memw($Rs) -= $Rt", - (L4_sub_memopw_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>, - Requires<[UseMEMOP]>; - -def : InstAlias<"memw($Rs) += #$U5", - (L4_iadd_memopw_io IntRegs:$Rs, 0, u5_0Imm:$U5), 0>, - Requires<[UseMEMOP]>; - -def : InstAlias<"memw($Rs) -= #$U5", - (L4_isub_memopw_io IntRegs:$Rs, 0, u5_0Imm:$U5), 0>, - Requires<[UseMEMOP]>; - -// -// Alias of: if ($Pv.new) memX($Rs) = $Rt -// to: if (p3.new) memX(r17 + #0) = $Rt -def : InstAlias<"if ($Pv.new) memb($Rs) = $Rt", - (S4_pstorerbtnew_io PredRegs:$Pv, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if ($Pv.new) memh($Rs) = $Rt", - (S4_pstorerhtnew_io PredRegs:$Pv, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if ($Pv.new) memh($Rs) = $Rt.h", - (S4_pstorerftnew_io PredRegs:$Pv, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if ($Pv.new) memw($Rs) = $Rt", - (S4_pstoreritnew_io PredRegs:$Pv, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if ($Pv.new) memd($Rs) = $Rtt", - (S4_pstorerdtnew_io - PredRegs:$Pv, IntRegs:$Rs, 0, DoubleRegs:$Rtt), 0>; - -def : InstAlias<"if (!$Pv.new) memb($Rs) = $Rt", - (S4_pstorerbfnew_io PredRegs:$Pv, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if (!$Pv.new) memh($Rs) = $Rt", - (S4_pstorerhfnew_io PredRegs:$Pv, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if (!$Pv.new) memh($Rs) = $Rt.h", - (S4_pstorerffnew_io PredRegs:$Pv, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if (!$Pv.new) memw($Rs) = $Rt", - (S4_pstorerifnew_io PredRegs:$Pv, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if (!$Pv.new) memd($Rs) = $Rtt", - (S4_pstorerdfnew_io - PredRegs:$Pv, IntRegs:$Rs, 0, DoubleRegs:$Rtt), 0>; - -// -// Alias of: if ($Pt.new) $Rd = memub($Rs) -- And if (!$Pt.new) ... -// to: if ($Pt.new) $Rd = memub($Rs + #$u6_0) -def : InstAlias<"if ($Pt.new) $Rd = memub($Rs)", - (L2_ploadrubtnew_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"if ($Pt.new) $Rd = memb($Rs)", - (L2_ploadrbtnew_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"if ($Pt.new) $Rd = memh($Rs)", - (L2_ploadrhtnew_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"if ($Pt.new) $Rd = memuh($Rs)", - (L2_ploadruhtnew_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"if ($Pt.new) $Rd = memw($Rs)", - (L2_ploadritnew_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"if ($Pt.new) $Rdd = memd($Rs)", - (L2_ploadrdtnew_io DoubleRegs:$Rdd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"if (!$Pt.new) $Rd = memub($Rs)", - (L2_ploadrubfnew_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"if (!$Pt.new) $Rd = memb($Rs)", - (L2_ploadrbfnew_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"if (!$Pt.new) $Rd = memh($Rs)", - (L2_ploadrhfnew_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"if (!$Pt.new) $Rd = memuh($Rs)", - (L2_ploadruhfnew_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"if (!$Pt.new) $Rd = memw($Rs)", - (L2_ploadrifnew_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"if (!$Pt.new) $Rdd = memd($Rs)", - (L2_ploadrdfnew_io DoubleRegs:$Rdd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"dcfetch($Rs)", - (Y2_dcfetchbo IntRegs:$Rs, 0), 0>; - -// Alias of some insn mappings, others must be handled by the parser -def : InstAlias<"$Pd=cmp.lt($Rs, $Rt)", - (C2_cmpgt PredRegs:$Pd, IntRegs:$Rt, IntRegs:$Rs), 0>; -def : InstAlias<"$Pd=cmp.ltu($Rs, $Rt)", - (C2_cmpgtu PredRegs:$Pd, IntRegs:$Rt, IntRegs:$Rs), 0>; - -// Rd=neg(Rs) is aliased to Rd=sub(#0,Rs) -def : InstAlias<"$Rd = neg($Rs)", - (A2_subri IntRegs:$Rd, 0, IntRegs:$Rs), 0>; -def : InstAlias<"$Rd=zxtb($Rs)", - (A2_andir IntRegs:$Rd, IntRegs:$Rs, 255)>; - -def : InstAlias<"m0 = $Rs", (A2_tfrrcr C6, IntRegs:$Rs)>; -def : InstAlias<"$Rd = m0", (A2_tfrcrr IntRegs:$Rd, C6)>; -def : InstAlias<"m1 = $Rs", (A2_tfrrcr C7, IntRegs:$Rs)>; -def : InstAlias<"$Rd = m1", (A2_tfrcrr IntRegs:$Rd, C7)>; - -def : InstAlias<"$Pd = $Ps", - (C2_or PredRegs:$Pd, PredRegs:$Ps, PredRegs:$Ps), 0>; - -def : InstAlias<"$Rdd = vaddb($Rss, $Rtt)", - (A2_vaddub DoubleRegs:$Rdd, DoubleRegs:$Rss, DoubleRegs:$Rtt), 1>; - -def : InstAlias<"$Rdd = vsubb($Rss,$Rtt)", - (A2_vsubub DoubleRegs:$Rdd, DoubleRegs:$Rss, DoubleRegs:$Rtt), 0>; - -def : InstAlias<"$Rd = mpyui($Rs,$Rt)", - (M2_mpyi IntRegs:$Rd, IntRegs:$Rs, IntRegs:$Rt), 0>; - -// Assembler mapped insns: cmp.lt(a,b) -> cmp.gt(b,a) -def : InstAlias<"$Pd=cmp.lt($Rs, $Rt)", - (C2_cmpgt PredRegs:$Pd, IntRegs:$Rt, IntRegs:$Rs), 0>; -def : InstAlias<"$Pd=cmp.ltu($Rs, $Rt)", - (C2_cmpgtu PredRegs:$Pd, IntRegs:$Rt, IntRegs:$Rs), 0>; - -// maps if (!Pu) jumpr Rs -> if (!Pu) jumpr:nt Rs -def : InstAlias<"if (!$Pu) jumpr $Rs", - (J2_jumprf PredRegs:$Pu, IntRegs:$Rs)>, - Requires<[HasV60T]>; - -// maps if (Pu) jumpr Rs -> if (Pu) jumpr:nt Rs -def : InstAlias<"if ($Pu) jumpr $Rs", - (J2_jumprt PredRegs:$Pu, IntRegs:$Rs)>, - Requires<[HasV60T]>; - -// maps if (!Pu) jump $r15_2 -> if (!Pu) jump:nt $r15_2 -def : InstAlias<"if (!$Pu) jump $r15_2", - (J2_jumpf PredRegs:$Pu, brtarget:$r15_2)>, - Requires<[HasV60T]>; - -// maps if (Pu) jump $r15_2 -> if (Pu) jump:nt $r15_2 -def : InstAlias<"if ($Pu) jump $r15_2", - (J2_jumpt PredRegs:$Pu, brtarget:$r15_2)>, - Requires<[HasV60T]>; - -def : InstAlias<"if ($src) jump $r15_2", - (J2_jumpt PredRegs:$src, brtarget:$r15_2), 0>; - -def : InstAlias<"if (!$src) jump $r15_2", - (J2_jumpf PredRegs:$src, brtarget:$r15_2), 0>; - -def : InstAlias<"if ($src1) jumpr $src2", - (J2_jumprt PredRegs:$src1, IntRegs:$src2), 0>; - -def : InstAlias<"if (!$src1) jumpr $src2", - (J2_jumprf PredRegs:$src1, IntRegs:$src2), 0>; - -// maps Vdd = Vss to Vdd = V6_vassignp(Vss) -def : InstAlias<"$Vdd = $Vss", - (V6_vassignp VecDblRegs:$Vdd, VecDblRegs:$Vss)>, - Requires<[HasV60T]>; - -// maps Vd = #0 to Vd = vxor(Vd, Vd) -def : InstAlias<"$Vd = #0", - (V6_vxor VectorRegs:$Vd, VectorRegs:$Vd, VectorRegs:$Vd)>, - Requires<[HasV60T]>; - -// maps Vdd = #0 to Vdd = vsub(Vdd, Vdd) -def : InstAlias<"$Vdd = #0", - (V6_vsubw_dv VecDblRegs:$Vdd, VecDblRegs:$Vdd, VecDblRegs:$Vdd)>, - Requires<[HasV60T]>; - -// maps "$Qd = vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd = vcmp.eq($Vu.h, $Vv.h)" -def : InstAlias<"$Qd = vcmp.eq($Vu.uh, $Vv.uh)", - (V6_veqh VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>, - Requires<[HasV60T]>; - -// maps "$Qd &= vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd &= vcmp.eq($Vu.h, $Vv.h)" -def : InstAlias<"$Qd &= vcmp.eq($Vu.uh, $Vv.uh)", - (V6_veqh_and VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>, - Requires<[HasV60T]>; - -// maps "$Qd |= vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd |= vcmp.eq($Vu.h, $Vv.h)" -def : InstAlias<"$Qd |= vcmp.eq($Vu.uh, $Vv.uh)", - (V6_veqh_or VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>, - Requires<[HasV60T]>; - -// maps "$Qd ^= vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd ^= vcmp.eq($Vu.h, $Vv.h)" -def : InstAlias<"$Qd ^= vcmp.eq($Vu.uh, $Vv.uh)", - (V6_veqh_xor VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>, - Requires<[HasV60T]>; - -// maps "$Qd = vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd = vcmp.eq($Vu.w, $Vv.w)" -def : InstAlias<"$Qd = vcmp.eq($Vu.uw, $Vv.uw)", - (V6_veqw VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>, - Requires<[HasV60T]>; - -// maps "$Qd &= vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd &= vcmp.eq($Vu.w, $Vv.w)" -def : InstAlias<"$Qd &= vcmp.eq($Vu.uw, $Vv.uw)", - (V6_veqw_and VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>, - Requires<[HasV60T]>; - -// maps "$Qd |= vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd |= vcmp.eq($Vu.w, $Vv.w)" -def : InstAlias<"$Qd |= vcmp.eq($Vu.uw, $Vv.uw)", - (V6_veqh_or VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>, - Requires<[HasV60T]>; - -// maps "$Qd ^= vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd ^= vcmp.eq($Vu.w, $Vv.w)" -def : InstAlias<"$Qd ^= vcmp.eq($Vu.uw, $Vv.uw)", - (V6_veqw_xor VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>, - Requires<[HasV60T]>; - -// maps "$Qd = vcmp.eq($Vu.ub, $Vv.ub)" -> "$Qd = vcmp.eq($Vu.b, $Vv.b)" -def : InstAlias<"$Qd = vcmp.eq($Vu.ub, $Vv.ub)", - (V6_veqb VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>, - Requires<[HasV60T]>; - -// maps "$Qd &= vcmp.eq($Vu.ub, $Vv.ub)" -> "$Qd &= vcmp.eq($Vu.b, $Vv.b)" -def : InstAlias<"$Qd &= vcmp.eq($Vu.ub, $Vv.ub)", - (V6_veqb_and VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>, - Requires<[HasV60T]>; - -// maps "$Qd |= vcmp.eq($Vu.ub, $Vv.ub)" -> "$Qd |= vcmp.eq($Vu.b, $Vv.b)" -def : InstAlias<"$Qd |= vcmp.eq($Vu.ub, $Vv.ub)", - (V6_veqb_or VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>, - Requires<[HasV60T]>; - -// maps "$Qd ^= vcmp.eq($Vu.ub, $Vv.ub)" -> "$Qd ^= vcmp.eq($Vu.b, $Vv.b)" -def : InstAlias<"$Qd ^= vcmp.eq($Vu.ub, $Vv.ub)", - (V6_veqb_xor VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>, - Requires<[HasV60T]>; - -// maps "$Rd.w = vextract($Vu, $Rs)" -> "$Rd = vextract($Vu, $Rs)" -def : InstAlias<"$Rd.w = vextract($Vu, $Rs)", - (V6_extractw IntRegs:$Rd, VectorRegs:$Vu, IntRegs:$Rs)>, - Requires<[HasV60T]>; - -// Mapping from vtrans2x2(Vy32,Vx32,Rt32) to vshuff(Vy32,Vx32,Rt32) -def : InstAlias<"vtrans2x2($Vy, $Vx, $Rt)", - (V6_vshuff VectorRegs:$Vy, VectorRegs:$Vx, IntRegs:$Rt)>, - Requires<[HasV60T]>; - -def : InstAlias<"$Vt=vmem($Rs)", - (V6_vL32b_ai VectorRegs:$Vt, IntRegs:$Rs, 0)>, - Requires<[HasV60T]>; - -def : InstAlias<"$Vt=vmem($Rs):nt", - (V6_vL32b_nt_ai VectorRegs:$Vt, IntRegs:$Rs, 0)>, - Requires<[HasV60T]>; - -def : InstAlias<"vmem($Rs)=$Vt", - (V6_vS32b_ai IntRegs:$Rs, 0, VectorRegs:$Vt)>, - Requires<[HasV60T]>; - -def : InstAlias<"vmem($Rs):nt=$Vt", - (V6_vS32b_nt_ai IntRegs:$Rs, 0, VectorRegs:$Vt)>, - Requires<[HasV60T]>; - -def : InstAlias<"vmem($Rs)=$Vt.new", - (V6_vS32b_new_ai IntRegs:$Rs, 0, VectorRegs:$Vt)>, - Requires<[HasV60T]>; - -def : InstAlias<"vmem($Rs):nt=$Vt.new", - (V6_vS32b_nt_new_ai IntRegs:$Rs, 0, VectorRegs:$Vt)>, - Requires<[HasV60T]>; - -def : InstAlias<"if ($Qv) vmem($Rs)=$Vt", - (V6_vS32b_qpred_ai VecPredRegs:$Qv, IntRegs:$Rs, 0, VectorRegs:$Vt)>, - Requires<[HasV60T]>; - -def : InstAlias<"if (!$Qv) vmem($Rs)=$Vt", - (V6_vS32b_nqpred_ai VecPredRegs:$Qv, IntRegs:$Rs, 0, VectorRegs:$Vt)>, - Requires<[HasV60T]>; - -def : InstAlias<"if ($Qv) vmem($Rs):nt=$Vt", - (V6_vS32b_nt_qpred_ai VecPredRegs:$Qv, IntRegs:$Rs, 0, VectorRegs:$Vt)>, - Requires<[HasV60T]>; - -def : InstAlias<"if (!$Qv) vmem($Rs):nt=$Vt", - (V6_vS32b_nt_nqpred_ai VecPredRegs:$Qv, IntRegs:$Rs, 0, VectorRegs:$Vt)>, - Requires<[HasV60T]>; - -def : InstAlias<"if ($Pv) vmem($Rs)=$Vt", - (V6_vS32b_pred_ai PredRegs:$Pv, IntRegs:$Rs, 0, VectorRegs:$Vt)>, - Requires<[HasV60T]>; - -def : InstAlias<"if (!$Pv) vmem($Rs)=$Vt", - (V6_vS32b_npred_ai PredRegs:$Pv, IntRegs:$Rs, 0, VectorRegs:$Vt)>, - Requires<[HasV60T]>; - -def : InstAlias<"if ($Pv) vmem($Rs):nt=$Vt", - (V6_vS32b_nt_pred_ai PredRegs:$Pv, IntRegs:$Rs, 0, VectorRegs:$Vt)>, - Requires<[HasV60T]>; - -def : InstAlias<"if (!$Pv) vmem($Rs):nt=$Vt", - (V6_vS32b_nt_npred_ai PredRegs:$Pv, IntRegs:$Rs, 0, VectorRegs:$Vt)>, - Requires<[HasV60T]>; - -def : InstAlias<"$Vt=vmemu($Rs)", - (V6_vL32Ub_ai VectorRegs:$Vt, IntRegs:$Rs, 0)>, - Requires<[HasV60T]>; - -def : InstAlias<"vmemu($Rs)=$Vt", - (V6_vS32Ub_ai IntRegs:$Rs, 0, VectorRegs:$Vt)>, - Requires<[HasV60T]>; - -def : InstAlias<"if ($Pv) vmemu($Rs)=$Vt", - (V6_vS32Ub_pred_ai PredRegs:$Pv, IntRegs:$Rs, 0, VectorRegs:$Vt)>, - Requires<[HasV60T]>; - -def : InstAlias<"if (!$Pv) vmemu($Rs)=$Vt", - (V6_vS32Ub_npred_ai PredRegs:$Pv, IntRegs:$Rs, 0, VectorRegs:$Vt)>, - Requires<[HasV60T]>; - - diff --git a/lib/Target/Hexagon/HexagonInstrEnc.td b/lib/Target/Hexagon/HexagonInstrEnc.td deleted file mode 100644 index 280832fd167..00000000000 --- a/lib/Target/Hexagon/HexagonInstrEnc.td +++ /dev/null @@ -1,1019 +0,0 @@ -class Enc_COPROC_VX_3op_v opc> : OpcodeHexagon { - bits<5> dst; - bits<5> src1; - bits<5> src2; - - let Inst{31-16} = { opc{14-4}, src2}; - let Inst{13-0} = { opc{3}, src1, opc{2-0}, dst}; -} - -class V6_vtmpyb_enc : Enc_COPROC_VX_3op_v<0b000110010000000>; -class V6_vtmpybus_enc : Enc_COPROC_VX_3op_v<0b000110010000001>; -class V6_vdmpyhb_enc : Enc_COPROC_VX_3op_v<0b000110010000010>; -class V6_vrmpyub_enc : Enc_COPROC_VX_3op_v<0b000110010000011>; -class V6_vrmpybus_enc : Enc_COPROC_VX_3op_v<0b000110010000100>; -class V6_vdsaduh_enc : Enc_COPROC_VX_3op_v<0b000110010000101>; -class V6_vdmpybus_enc : Enc_COPROC_VX_3op_v<0b000110010000110>; -class V6_vdmpybus_dv_enc : Enc_COPROC_VX_3op_v<0b000110010000111>; -class V6_vtmpyb_acc_enc : Enc_COPROC_VX_3op_v<0b000110010001000>; -class V6_vtmpybus_acc_enc : Enc_COPROC_VX_3op_v<0b000110010001001>; -class V6_vtmpyhb_acc_enc : Enc_COPROC_VX_3op_v<0b000110010001010>; -class V6_vdmpyhb_acc_enc : Enc_COPROC_VX_3op_v<0b000110010001011>; -class V6_vrmpyub_acc_enc : Enc_COPROC_VX_3op_v<0b000110010001100>; -class V6_vrmpybus_acc_enc : Enc_COPROC_VX_3op_v<0b000110010001101>; -class V6_vdmpybus_acc_enc : Enc_COPROC_VX_3op_v<0b000110010001110>; -class V6_vdmpybus_dv_acc_enc : Enc_COPROC_VX_3op_v<0b000110010001111>; -class V6_vdmpyhsusat_enc : Enc_COPROC_VX_3op_v<0b000110010010000>; -class V6_vdmpyhsuisat_enc : Enc_COPROC_VX_3op_v<0b000110010010001>; -class V6_vdmpyhsat_enc : Enc_COPROC_VX_3op_v<0b000110010010010>; -class V6_vdmpyhisat_enc : Enc_COPROC_VX_3op_v<0b000110010010011>; -class V6_vdmpyhb_dv_enc : Enc_COPROC_VX_3op_v<0b000110010010100>; -class V6_vmpybus_enc : Enc_COPROC_VX_3op_v<0b000110010010101>; -class V6_vmpabus_enc : Enc_COPROC_VX_3op_v<0b000110010010110>; -class V6_vmpahb_enc : Enc_COPROC_VX_3op_v<0b000110010010111>; -class V6_vdmpyhsusat_acc_enc : Enc_COPROC_VX_3op_v<0b000110010011000>; -class V6_vdmpyhsuisat_acc_enc : Enc_COPROC_VX_3op_v<0b000110010011001>; -class V6_vdmpyhisat_acc_enc : Enc_COPROC_VX_3op_v<0b000110010011010>; -class V6_vdmpyhsat_acc_enc : Enc_COPROC_VX_3op_v<0b000110010011011>; -class V6_vdmpyhb_dv_acc_enc : Enc_COPROC_VX_3op_v<0b000110010011100>; -class V6_vmpybus_acc_enc : Enc_COPROC_VX_3op_v<0b000110010011101>; -class V6_vmpabus_acc_enc : Enc_COPROC_VX_3op_v<0b000110010011110>; -class V6_vmpahb_acc_enc : Enc_COPROC_VX_3op_v<0b000110010011111>; -class V6_vmpyh_enc : Enc_COPROC_VX_3op_v<0b000110010100000>; -class V6_vmpyhss_enc : Enc_COPROC_VX_3op_v<0b000110010100001>; -class V6_vmpyhsrs_enc : Enc_COPROC_VX_3op_v<0b000110010100010>; -class V6_vmpyuh_enc : Enc_COPROC_VX_3op_v<0b000110010100011>; -class V6_vmpyhsat_acc_enc : Enc_COPROC_VX_3op_v<0b000110010101000>; -class V6_vmpyuh_acc_enc : Enc_COPROC_VX_3op_v<0b000110010101001>; -class V6_vmpyiwb_acc_enc : Enc_COPROC_VX_3op_v<0b000110010101010>; -class V6_vmpyiwh_acc_enc : Enc_COPROC_VX_3op_v<0b000110010101011>; -class V6_vmpyihb_enc : Enc_COPROC_VX_3op_v<0b000110010110000>; -class V6_vror_enc : Enc_COPROC_VX_3op_v<0b000110010110001>; -class V6_vasrw_enc : Enc_COPROC_VX_3op_v<0b000110010110101>; -class V6_vasrh_enc : Enc_COPROC_VX_3op_v<0b000110010110110>; -class V6_vaslw_enc : Enc_COPROC_VX_3op_v<0b000110010110111>; -class V6_vdsaduh_acc_enc : Enc_COPROC_VX_3op_v<0b000110010111000>; -class V6_vmpyihb_acc_enc : Enc_COPROC_VX_3op_v<0b000110010111001>; -class V6_vaslw_acc_enc : Enc_COPROC_VX_3op_v<0b000110010111010>; -class V6_vasrw_acc_enc : Enc_COPROC_VX_3op_v<0b000110010111101>; -class V6_vaslh_enc : Enc_COPROC_VX_3op_v<0b000110011000000>; -class V6_vlsrw_enc : Enc_COPROC_VX_3op_v<0b000110011000001>; -class V6_vlsrh_enc : Enc_COPROC_VX_3op_v<0b000110011000010>; -class V6_vmpyiwh_enc : Enc_COPROC_VX_3op_v<0b000110011000111>; -class V6_vmpyub_acc_enc : Enc_COPROC_VX_3op_v<0b000110011001000>; -class V6_vmpyiwb_enc : Enc_COPROC_VX_3op_v<0b000110011010000>; -class V6_vtmpyhb_enc : Enc_COPROC_VX_3op_v<0b000110011010100>; -class V6_vmpyub_enc : Enc_COPROC_VX_3op_v<0b000110011100000>; -class V6_vrmpyubv_enc : Enc_COPROC_VX_3op_v<0b000111000000000>; -class V6_vrmpybv_enc : Enc_COPROC_VX_3op_v<0b000111000000001>; -class V6_vrmpybusv_enc : Enc_COPROC_VX_3op_v<0b000111000000010>; -class V6_vdmpyhvsat_enc : Enc_COPROC_VX_3op_v<0b000111000000011>; -class V6_vmpybv_enc : Enc_COPROC_VX_3op_v<0b000111000000100>; -class V6_vmpyubv_enc : Enc_COPROC_VX_3op_v<0b000111000000101>; -class V6_vmpybusv_enc : Enc_COPROC_VX_3op_v<0b000111000000110>; -class V6_vmpyhv_enc : Enc_COPROC_VX_3op_v<0b000111000000111>; -class V6_vrmpyubv_acc_enc : Enc_COPROC_VX_3op_v<0b000111000001000>; -class V6_vrmpybv_acc_enc : Enc_COPROC_VX_3op_v<0b000111000001001>; -class V6_vrmpybusv_acc_enc : Enc_COPROC_VX_3op_v<0b000111000001010>; -class V6_vdmpyhvsat_acc_enc : Enc_COPROC_VX_3op_v<0b000111000001011>; -class V6_vmpybv_acc_enc : Enc_COPROC_VX_3op_v<0b000111000001100>; -class V6_vmpyubv_acc_enc : Enc_COPROC_VX_3op_v<0b000111000001101>; -class V6_vmpybusv_acc_enc : Enc_COPROC_VX_3op_v<0b000111000001110>; -class V6_vmpyhv_acc_enc : Enc_COPROC_VX_3op_v<0b000111000001111>; -class V6_vmpyuhv_enc : Enc_COPROC_VX_3op_v<0b000111000010000>; -class V6_vmpyhvsrs_enc : Enc_COPROC_VX_3op_v<0b000111000010001>; -class V6_vmpyhus_enc : Enc_COPROC_VX_3op_v<0b000111000010010>; -class V6_vmpabusv_enc : Enc_COPROC_VX_3op_v<0b000111000010011>; -class V6_vmpyih_enc : Enc_COPROC_VX_3op_v<0b000111000010100>; -class V6_vand_enc : Enc_COPROC_VX_3op_v<0b000111000010101>; -class V6_vor_enc : Enc_COPROC_VX_3op_v<0b000111000010110>; -class V6_vxor_enc : Enc_COPROC_VX_3op_v<0b000111000010111>; -class V6_vmpyuhv_acc_enc : Enc_COPROC_VX_3op_v<0b000111000011000>; -class V6_vmpyhus_acc_enc : Enc_COPROC_VX_3op_v<0b000111000011001>; -class V6_vmpyih_acc_enc : Enc_COPROC_VX_3op_v<0b000111000011100>; -class V6_vmpyiewuh_acc_enc : Enc_COPROC_VX_3op_v<0b000111000011101>; -class V6_vmpyowh_sacc_enc : Enc_COPROC_VX_3op_v<0b000111000011110>; -class V6_vmpyowh_rnd_sacc_enc : Enc_COPROC_VX_3op_v<0b000111000011111>; -class V6_vaddw_enc : Enc_COPROC_VX_3op_v<0b000111000100000>; -class V6_vaddubsat_enc : Enc_COPROC_VX_3op_v<0b000111000100001>; -class V6_vadduhsat_enc : Enc_COPROC_VX_3op_v<0b000111000100010>; -class V6_vaddhsat_enc : Enc_COPROC_VX_3op_v<0b000111000100011>; -class V6_vaddwsat_enc : Enc_COPROC_VX_3op_v<0b000111000100100>; -class V6_vsubb_enc : Enc_COPROC_VX_3op_v<0b000111000100101>; -class V6_vsubh_enc : Enc_COPROC_VX_3op_v<0b000111000100110>; -class V6_vsubw_enc : Enc_COPROC_VX_3op_v<0b000111000100111>; -class V6_vmpyiewh_acc_enc : Enc_COPROC_VX_3op_v<0b000111000101000>; -class V6_vsububsat_enc : Enc_COPROC_VX_3op_v<0b000111000110000>; -class V6_vsubuhsat_enc : Enc_COPROC_VX_3op_v<0b000111000110001>; -class V6_vsubhsat_enc : Enc_COPROC_VX_3op_v<0b000111000110010>; -class V6_vsubwsat_enc : Enc_COPROC_VX_3op_v<0b000111000110011>; -class V6_vaddb_dv_enc : Enc_COPROC_VX_3op_v<0b000111000110100>; -class V6_vaddh_dv_enc : Enc_COPROC_VX_3op_v<0b000111000110101>; -class V6_vaddw_dv_enc : Enc_COPROC_VX_3op_v<0b000111000110110>; -class V6_vaddubsat_dv_enc : Enc_COPROC_VX_3op_v<0b000111000110111>; -class V6_vadduhsat_dv_enc : Enc_COPROC_VX_3op_v<0b000111001000000>; -class V6_vaddhsat_dv_enc : Enc_COPROC_VX_3op_v<0b000111001000001>; -class V6_vaddwsat_dv_enc : Enc_COPROC_VX_3op_v<0b000111001000010>; -class V6_vsubb_dv_enc : Enc_COPROC_VX_3op_v<0b000111001000011>; -class V6_vsubh_dv_enc : Enc_COPROC_VX_3op_v<0b000111001000100>; -class V6_vsubw_dv_enc : Enc_COPROC_VX_3op_v<0b000111001000101>; -class V6_vsububsat_dv_enc : Enc_COPROC_VX_3op_v<0b000111001000110>; -class V6_vsubuhsat_dv_enc : Enc_COPROC_VX_3op_v<0b000111001000111>; -class V6_vsubhsat_dv_enc : Enc_COPROC_VX_3op_v<0b000111001010000>; -class V6_vsubwsat_dv_enc : Enc_COPROC_VX_3op_v<0b000111001010001>; -class V6_vaddubh_enc : Enc_COPROC_VX_3op_v<0b000111001010010>; -class V6_vadduhw_enc : Enc_COPROC_VX_3op_v<0b000111001010011>; -class V6_vaddhw_enc : Enc_COPROC_VX_3op_v<0b000111001010100>; -class V6_vsububh_enc : Enc_COPROC_VX_3op_v<0b000111001010101>; -class V6_vsubuhw_enc : Enc_COPROC_VX_3op_v<0b000111001010110>; -class V6_vsubhw_enc : Enc_COPROC_VX_3op_v<0b000111001010111>; -class V6_vabsdiffub_enc : Enc_COPROC_VX_3op_v<0b000111001100000>; -class V6_vabsdiffh_enc : Enc_COPROC_VX_3op_v<0b000111001100001>; -class V6_vabsdiffuh_enc : Enc_COPROC_VX_3op_v<0b000111001100010>; -class V6_vabsdiffw_enc : Enc_COPROC_VX_3op_v<0b000111001100011>; -class V6_vavgub_enc : Enc_COPROC_VX_3op_v<0b000111001100100>; -class V6_vavguh_enc : Enc_COPROC_VX_3op_v<0b000111001100101>; -class V6_vavgh_enc : Enc_COPROC_VX_3op_v<0b000111001100110>; -class V6_vavgw_enc : Enc_COPROC_VX_3op_v<0b000111001100111>; -class V6_vnavgub_enc : Enc_COPROC_VX_3op_v<0b000111001110000>; -class V6_vnavgh_enc : Enc_COPROC_VX_3op_v<0b000111001110001>; -class V6_vnavgw_enc : Enc_COPROC_VX_3op_v<0b000111001110010>; -class V6_vavgubrnd_enc : Enc_COPROC_VX_3op_v<0b000111001110011>; -class V6_vavguhrnd_enc : Enc_COPROC_VX_3op_v<0b000111001110100>; -class V6_vavghrnd_enc : Enc_COPROC_VX_3op_v<0b000111001110101>; -class V6_vavgwrnd_enc : Enc_COPROC_VX_3op_v<0b000111001110110>; -class V6_vmpabuuv_enc : Enc_COPROC_VX_3op_v<0b000111001110111>; -class V6_vminub_enc : Enc_COPROC_VX_3op_v<0b000111110000001>; -class V6_vminuh_enc : Enc_COPROC_VX_3op_v<0b000111110000010>; -class V6_vminh_enc : Enc_COPROC_VX_3op_v<0b000111110000011>; -class V6_vminw_enc : Enc_COPROC_VX_3op_v<0b000111110000100>; -class V6_vmaxub_enc : Enc_COPROC_VX_3op_v<0b000111110000101>; -class V6_vmaxuh_enc : Enc_COPROC_VX_3op_v<0b000111110000110>; -class V6_vmaxh_enc : Enc_COPROC_VX_3op_v<0b000111110000111>; -class V6_vmaxw_enc : Enc_COPROC_VX_3op_v<0b000111110010000>; -class V6_vdelta_enc : Enc_COPROC_VX_3op_v<0b000111110010001>; -class V6_vrdelta_enc : Enc_COPROC_VX_3op_v<0b000111110010011>; -class V6_vdealb4w_enc : Enc_COPROC_VX_3op_v<0b000111110010111>; -class V6_vmpyowh_rnd_enc : Enc_COPROC_VX_3op_v<0b000111110100000>; -class V6_vshuffeb_enc : Enc_COPROC_VX_3op_v<0b000111110100001>; -class V6_vshuffob_enc : Enc_COPROC_VX_3op_v<0b000111110100010>; -class V6_vshufeh_enc : Enc_COPROC_VX_3op_v<0b000111110100011>; -class V6_vshufoh_enc : Enc_COPROC_VX_3op_v<0b000111110100100>; -class V6_vshufoeh_enc : Enc_COPROC_VX_3op_v<0b000111110100101>; -class V6_vshufoeb_enc : Enc_COPROC_VX_3op_v<0b000111110100110>; -class V6_vcombine_enc : Enc_COPROC_VX_3op_v<0b000111110100111>; -class V6_vmpyieoh_enc : Enc_COPROC_VX_3op_v<0b000111110110000>; -class V6_vsathub_enc : Enc_COPROC_VX_3op_v<0b000111110110010>; -class V6_vsatwh_enc : Enc_COPROC_VX_3op_v<0b000111110110011>; -class V6_vroundwh_enc : Enc_COPROC_VX_3op_v<0b000111110110100>; -class V6_vroundwuh_enc : Enc_COPROC_VX_3op_v<0b000111110110101>; -class V6_vroundhb_enc : Enc_COPROC_VX_3op_v<0b000111110110110>; -class V6_vroundhub_enc : Enc_COPROC_VX_3op_v<0b000111110110111>; -class V6_vasrwv_enc : Enc_COPROC_VX_3op_v<0b000111111010000>; -class V6_vlsrwv_enc : Enc_COPROC_VX_3op_v<0b000111111010001>; -class V6_vlsrhv_enc : Enc_COPROC_VX_3op_v<0b000111111010010>; -class V6_vasrhv_enc : Enc_COPROC_VX_3op_v<0b000111111010011>; -class V6_vaslwv_enc : Enc_COPROC_VX_3op_v<0b000111111010100>; -class V6_vaslhv_enc : Enc_COPROC_VX_3op_v<0b000111111010101>; -class V6_vaddb_enc : Enc_COPROC_VX_3op_v<0b000111111010110>; -class V6_vaddh_enc : Enc_COPROC_VX_3op_v<0b000111111010111>; -class V6_vmpyiewuh_enc : Enc_COPROC_VX_3op_v<0b000111111100000>; -class V6_vmpyiowh_enc : Enc_COPROC_VX_3op_v<0b000111111100001>; -class V6_vpackeb_enc : Enc_COPROC_VX_3op_v<0b000111111100010>; -class V6_vpackeh_enc : Enc_COPROC_VX_3op_v<0b000111111100011>; -class V6_vpackhub_sat_enc : Enc_COPROC_VX_3op_v<0b000111111100101>; -class V6_vpackhb_sat_enc : Enc_COPROC_VX_3op_v<0b000111111100110>; -class V6_vpackwuh_sat_enc : Enc_COPROC_VX_3op_v<0b000111111100111>; -class V6_vpackwh_sat_enc : Enc_COPROC_VX_3op_v<0b000111111110000>; -class V6_vpackob_enc : Enc_COPROC_VX_3op_v<0b000111111110001>; -class V6_vpackoh_enc : Enc_COPROC_VX_3op_v<0b000111111110010>; -class V6_vmpyewuh_enc : Enc_COPROC_VX_3op_v<0b000111111110101>; -class V6_vmpyowh_enc : Enc_COPROC_VX_3op_v<0b000111111110111>; -class V6_extractw_enc : Enc_COPROC_VX_3op_v<0b100100100000001>; -class M6_vabsdiffub_enc : Enc_COPROC_VX_3op_v<0b111010001010000>; -class M6_vabsdiffb_enc : Enc_COPROC_VX_3op_v<0b111010001110000>; - -class Enc_COPROC_VX_cmp opc> : OpcodeHexagon { - bits<2> dst; - bits<5> src1; - bits<5> src2; - - let Inst{31-16} = { 0b00011, opc{12-7}, src2{4-0} }; - let Inst{13-0} = { opc{6}, src1{4-0}, opc{5-0}, dst{1-0} }; -} - -class V6_vandvrt_acc_enc : Enc_COPROC_VX_cmp<0b0010111100000>; -class V6_vandvrt_enc : Enc_COPROC_VX_cmp<0b0011010010010>; -class V6_veqb_and_enc : Enc_COPROC_VX_cmp<0b1001001000000>; -class V6_veqh_and_enc : Enc_COPROC_VX_cmp<0b1001001000001>; -class V6_veqw_and_enc : Enc_COPROC_VX_cmp<0b1001001000010>; -class V6_vgtb_and_enc : Enc_COPROC_VX_cmp<0b1001001000100>; -class V6_vgth_and_enc : Enc_COPROC_VX_cmp<0b1001001000101>; -class V6_vgtw_and_enc : Enc_COPROC_VX_cmp<0b1001001000110>; -class V6_vgtub_and_enc : Enc_COPROC_VX_cmp<0b1001001001000>; -class V6_vgtuh_and_enc : Enc_COPROC_VX_cmp<0b1001001001001>; -class V6_vgtuw_and_enc : Enc_COPROC_VX_cmp<0b1001001001010>; -class V6_veqb_or_enc : Enc_COPROC_VX_cmp<0b1001001010000>; -class V6_veqh_or_enc : Enc_COPROC_VX_cmp<0b1001001010001>; -class V6_veqw_or_enc : Enc_COPROC_VX_cmp<0b1001001010010>; -class V6_vgtb_or_enc : Enc_COPROC_VX_cmp<0b1001001010100>; -class V6_vgth_or_enc : Enc_COPROC_VX_cmp<0b1001001010101>; -class V6_vgtw_or_enc : Enc_COPROC_VX_cmp<0b1001001010110>; -class V6_vgtub_or_enc : Enc_COPROC_VX_cmp<0b1001001011000>; -class V6_vgtuh_or_enc : Enc_COPROC_VX_cmp<0b1001001011001>; -class V6_vgtuw_or_enc : Enc_COPROC_VX_cmp<0b1001001011010>; -class V6_veqb_xor_enc : Enc_COPROC_VX_cmp<0b1001001100000>; -class V6_veqh_xor_enc : Enc_COPROC_VX_cmp<0b1001001100001>; -class V6_veqw_xor_enc : Enc_COPROC_VX_cmp<0b1001001100010>; -class V6_vgtb_xor_enc : Enc_COPROC_VX_cmp<0b1001001100100>; -class V6_vgth_xor_enc : Enc_COPROC_VX_cmp<0b1001001100101>; -class V6_vgtw_xor_enc : Enc_COPROC_VX_cmp<0b1001001100110>; -class V6_vgtub_xor_enc : Enc_COPROC_VX_cmp<0b1001001101000>; -class V6_vgtuh_xor_enc : Enc_COPROC_VX_cmp<0b1001001101001>; -class V6_vgtuw_xor_enc : Enc_COPROC_VX_cmp<0b1001001101010>; -class V6_veqb_enc : Enc_COPROC_VX_cmp<0b1111000000000>; -class V6_veqh_enc : Enc_COPROC_VX_cmp<0b1111000000001>; -class V6_veqw_enc : Enc_COPROC_VX_cmp<0b1111000000010>; -class V6_vgtb_enc : Enc_COPROC_VX_cmp<0b1111000000100>; -class V6_vgth_enc : Enc_COPROC_VX_cmp<0b1111000000101>; -class V6_vgtw_enc : Enc_COPROC_VX_cmp<0b1111000000110>; -class V6_vgtub_enc : Enc_COPROC_VX_cmp<0b1111000001000>; -class V6_vgtuh_enc : Enc_COPROC_VX_cmp<0b1111000001001>; -class V6_vgtuw_enc : Enc_COPROC_VX_cmp<0b1111000001010>; - -class Enc_COPROC_VX_p2op opc> : OpcodeHexagon { - bits<2> src1; - bits<5> dst; - bits<5> src2; - - let Inst{31-16} = { 0b00011110, src1{1-0}, 0b0000, opc{4-3} }; - let Inst{13-0} = { 1, src2{4-0}, opc{2-0}, dst{4-0} }; -} - -class V6_vaddbq_enc : Enc_COPROC_VX_p2op<0b01000>; -class V6_vaddhq_enc : Enc_COPROC_VX_p2op<0b01001>; -class V6_vaddwq_enc : Enc_COPROC_VX_p2op<0b01010>; -class V6_vaddbnq_enc : Enc_COPROC_VX_p2op<0b01011>; -class V6_vaddhnq_enc : Enc_COPROC_VX_p2op<0b01100>; -class V6_vaddwnq_enc : Enc_COPROC_VX_p2op<0b01101>; -class V6_vsubbq_enc : Enc_COPROC_VX_p2op<0b01110>; -class V6_vsubhq_enc : Enc_COPROC_VX_p2op<0b01111>; -class V6_vsubwq_enc : Enc_COPROC_VX_p2op<0b10000>; -class V6_vsubbnq_enc : Enc_COPROC_VX_p2op<0b10001>; -class V6_vsubhnq_enc : Enc_COPROC_VX_p2op<0b10010>; -class V6_vsubwnq_enc : Enc_COPROC_VX_p2op<0b10011>; - -class Enc_COPROC_VX_2op opc> : OpcodeHexagon { - bits<5> dst; - bits<5> src1; - - let Inst{31-16} = { 0b00011110000000, opc{5-4} }; - let Inst{13-0} = { opc{3}, src1{4-0}, opc{2-0}, dst{4-0} }; -} - -class V6_vabsh_enc : Enc_COPROC_VX_2op<0b000000>; -class V6_vabsh_sat_enc : Enc_COPROC_VX_2op<0b000001>; -class V6_vabsw_enc : Enc_COPROC_VX_2op<0b000010>; -class V6_vabsw_sat_enc : Enc_COPROC_VX_2op<0b000011>; -class V6_vnot_enc : Enc_COPROC_VX_2op<0b000100>; -class V6_vdealh_enc : Enc_COPROC_VX_2op<0b000110>; -class V6_vdealb_enc : Enc_COPROC_VX_2op<0b000111>; -class V6_vunpackob_enc : Enc_COPROC_VX_2op<0b001000>; -class V6_vunpackoh_enc : Enc_COPROC_VX_2op<0b001001>; -class V6_vunpackub_enc : Enc_COPROC_VX_2op<0b010000>; -class V6_vunpackuh_enc : Enc_COPROC_VX_2op<0b010001>; -class V6_vunpackb_enc : Enc_COPROC_VX_2op<0b010010>; -class V6_vunpackh_enc : Enc_COPROC_VX_2op<0b010011>; -class V6_vshuffh_enc : Enc_COPROC_VX_2op<0b010111>; -class V6_vshuffb_enc : Enc_COPROC_VX_2op<0b100000>; -class V6_vzb_enc : Enc_COPROC_VX_2op<0b100001>; -class V6_vzh_enc : Enc_COPROC_VX_2op<0b100010>; -class V6_vsb_enc : Enc_COPROC_VX_2op<0b100011>; -class V6_vsh_enc : Enc_COPROC_VX_2op<0b100100>; -class V6_vcl0w_enc : Enc_COPROC_VX_2op<0b100101>; -class V6_vpopcounth_enc : Enc_COPROC_VX_2op<0b100110>; -class V6_vcl0h_enc : Enc_COPROC_VX_2op<0b100111>; -class V6_vnormamtw_enc : Enc_COPROC_VX_2op<0b110100>; -class V6_vnormamth_enc : Enc_COPROC_VX_2op<0b110101>; -class V6_vassign_enc : Enc_COPROC_VX_2op<0b111111>; - -class Enc_COPROC_VMEM_vL32_b_ai opc> : OpcodeHexagon { - bits<5> dst; - bits<5> src1; - bits<10> src2; - bits<4> src2_vector; - - let src2_vector = src2{9-6}; - let Inst{31-16} = { 0b001010000, opc{3}, 0, src1{4-0} }; - let Inst{13-0} = { src2_vector{3}, 0b00, src2_vector{2-0}, opc{2-0}, dst{4-0} }; -} - -class V6_vL32b_ai_enc : Enc_COPROC_VMEM_vL32_b_ai<0b0000>; -class V6_vL32b_cur_ai_enc : Enc_COPROC_VMEM_vL32_b_ai<0b0001>; -class V6_vL32b_tmp_ai_enc : Enc_COPROC_VMEM_vL32_b_ai<0b0010>; -class V6_vL32Ub_ai_enc : Enc_COPROC_VMEM_vL32_b_ai<0b0111>; -class V6_vL32b_nt_ai_enc : Enc_COPROC_VMEM_vL32_b_ai<0b1000>; -class V6_vL32b_nt_cur_ai_enc : Enc_COPROC_VMEM_vL32_b_ai<0b1001>; -class V6_vL32b_nt_tmp_ai_enc : Enc_COPROC_VMEM_vL32_b_ai<0b1010>; - -class Enc_COPROC_VMEM_vL32_b_ai_128B opc> : OpcodeHexagon { - bits<5> dst; - bits<5> src1; - bits<11> src2; - bits<4> src2_vector; - - let src2_vector = src2{10-7}; - let Inst{31-16} = { 0b001010000, opc{3}, 0, src1{4-0} }; - let Inst{13-0} = { src2_vector{3}, 0b00, src2_vector{2-0}, opc{2-0}, dst{4-0} }; -} - -class V6_vL32b_ai_128B_enc : Enc_COPROC_VMEM_vL32_b_ai_128B<0b0000>; -class V6_vL32b_cur_ai_128B_enc : Enc_COPROC_VMEM_vL32_b_ai_128B<0b0001>; -class V6_vL32b_tmp_ai_128B_enc : Enc_COPROC_VMEM_vL32_b_ai_128B<0b0010>; -class V6_vL32Ub_ai_128B_enc : Enc_COPROC_VMEM_vL32_b_ai_128B<0b0111>; -class V6_vL32b_nt_ai_128B_enc : Enc_COPROC_VMEM_vL32_b_ai_128B<0b1000>; -class V6_vL32b_nt_cur_ai_128B_enc : Enc_COPROC_VMEM_vL32_b_ai_128B<0b1001>; -class V6_vL32b_nt_tmp_ai_128B_enc : Enc_COPROC_VMEM_vL32_b_ai_128B<0b1010>; - -class Enc_COPROC_VMEM_vS32_b_ai_64B opc> : OpcodeHexagon { - bits<5> src1; - bits<10> src2; - bits<4> src2_vector; - bits<5> src3; - - let src2_vector = src2{9-6}; - let Inst{31-16} = { 0b001010000, opc{3}, 1, src1{4-0} }; - let Inst{13-0} = { src2_vector{3}, 0b00, src2_vector{2-0}, opc{2-0}, src3{4-0} }; -} - -class Enc_COPROC_VMEM_vS32_b_ai_128B opc> : OpcodeHexagon { - bits<5> src1; - bits<11> src2; - bits<4> src2_vector; - bits<5> src3; - - let src2_vector = src2{10-7}; - let Inst{31-16} = { 0b001010000, opc{3}, 1, src1{4-0} }; - let Inst{13-0} = { src2_vector{3}, 0b00, src2_vector{2-0}, opc{2-0}, src3{4-0} }; -} - -class V6_vS32b_ai_enc : Enc_COPROC_VMEM_vS32_b_ai_64B<0b0000>; -class V6_vS32Ub_ai_enc : Enc_COPROC_VMEM_vS32_b_ai_64B<0b0111>; -class V6_vS32b_nt_ai_enc : Enc_COPROC_VMEM_vS32_b_ai_64B<0b1000>; - -class V6_vS32b_ai_128B_enc : Enc_COPROC_VMEM_vS32_b_ai_128B<0b0000>; -class V6_vS32Ub_ai_128B_enc : Enc_COPROC_VMEM_vS32_b_ai_128B<0b0111>; -class V6_vS32b_nt_ai_128B_enc : Enc_COPROC_VMEM_vS32_b_ai_128B<0b1000>; - -class Enc_COPROC_VMEM_vS32b_n_ew_ai_64B opc> : OpcodeHexagon { - bits<5> src1; - bits<10> src2; - bits<4> src2_vector; - bits<3> src3; - - let src2_vector = src2{9-6}; - let Inst{31-16} = { 0b001010000, opc{0}, 1, src1{4-0} }; - let Inst{13-0} = { src2_vector{3}, 0b00, src2_vector{2-0}, 0b00100, src3{2-0} }; -} - -class V6_vS32b_new_ai_enc : Enc_COPROC_VMEM_vS32b_n_ew_ai_64B<0>; -class V6_vS32b_nt_new_ai_enc : Enc_COPROC_VMEM_vS32b_n_ew_ai_64B<1>; - -class Enc_COPROC_VMEM_vS32b_n_ew_ai_128B opc> : OpcodeHexagon { - bits<5> src1; - bits<11> src2; - bits<4> src2_vector; - bits<3> src3; - - let src2_vector = src2{10-7}; - let Inst{31-16} = { 0b001010000, opc{0}, 1, src1{4-0} }; - let Inst{13-0} = { src2_vector{3}, 0b00, src2_vector{2-0}, 0b00100, src3{2-0} }; -} - -class V6_vS32b_new_ai_128B_enc : Enc_COPROC_VMEM_vS32b_n_ew_ai_128B<0>; -class V6_vS32b_nt_new_ai_128B_enc : Enc_COPROC_VMEM_vS32b_n_ew_ai_128B<1>; - -class Enc_COPROC_VMEM_vS32_b_pred_ai opc> : OpcodeHexagon { - bits<2> src1; - bits<5> src2; - bits<10> src3; - bits<4> src3_vector; - bits<5> src4; - - let src3_vector = src3{9-6}; - let Inst{31-16} = { 0b001010001, opc{4-3}, src2{4-0} }; - let Inst{13-0} = { src3_vector{3}, src1{1-0}, src3_vector{2-0}, opc{2-0}, src4{4-0} }; -} - -class Enc_COPROC_VMEM_vS32_b_pred_ai_128B opc> : OpcodeHexagon { - bits<2> src1; - bits<5> src2; - bits<11> src3; - bits<4> src3_vector; - bits<5> src4; - - let src3_vector = src3{10-7}; - let Inst{31-16} = { 0b001010001, opc{4-3}, src2{4-0} }; - let Inst{13-0} = { src3_vector{3}, src1{1-0}, src3_vector{2-0}, opc{2-0}, src4{4-0} }; -} - -class V6_vS32b_qpred_ai_enc : Enc_COPROC_VMEM_vS32_b_pred_ai<0b00000>; -class V6_vS32b_nqpred_ai_enc : Enc_COPROC_VMEM_vS32_b_pred_ai<0b00001>; -class V6_vS32b_pred_ai_enc : Enc_COPROC_VMEM_vS32_b_pred_ai<0b01000>; -class V6_vS32b_npred_ai_enc : Enc_COPROC_VMEM_vS32_b_pred_ai<0b01001>; -class V6_vS32Ub_pred_ai_enc : Enc_COPROC_VMEM_vS32_b_pred_ai<0b01110>; -class V6_vS32Ub_npred_ai_enc : Enc_COPROC_VMEM_vS32_b_pred_ai<0b01111>; -class V6_vS32b_nt_qpred_ai_enc : Enc_COPROC_VMEM_vS32_b_pred_ai<0b10000>; -class V6_vS32b_nt_nqpred_ai_enc : Enc_COPROC_VMEM_vS32_b_pred_ai<0b10001>; -class V6_vS32b_nt_pred_ai_enc : Enc_COPROC_VMEM_vS32_b_pred_ai<0b11000>; -class V6_vS32b_nt_npred_ai_enc : Enc_COPROC_VMEM_vS32_b_pred_ai<0b11001>; - -class V6_vS32b_qpred_ai_128B_enc : Enc_COPROC_VMEM_vS32_b_pred_ai_128B<0b00000>; -class V6_vS32b_nqpred_ai_128B_enc : Enc_COPROC_VMEM_vS32_b_pred_ai_128B<0b00001>; -class V6_vS32b_pred_ai_128B_enc : Enc_COPROC_VMEM_vS32_b_pred_ai_128B<0b01000>; -class V6_vS32b_npred_ai_128B_enc : Enc_COPROC_VMEM_vS32_b_pred_ai_128B<0b01001>; -class V6_vS32Ub_pred_ai_128B_enc : Enc_COPROC_VMEM_vS32_b_pred_ai_128B<0b01110>; -class V6_vS32Ub_npred_ai_128B_enc : Enc_COPROC_VMEM_vS32_b_pred_ai_128B<0b01111>; -class V6_vS32b_nt_qpred_ai_128B_enc : Enc_COPROC_VMEM_vS32_b_pred_ai_128B<0b10000>; -class V6_vS32b_nt_nqpred_ai_128B_enc : Enc_COPROC_VMEM_vS32_b_pred_ai_128B<0b10001>; -class V6_vS32b_nt_pred_ai_128B_enc : Enc_COPROC_VMEM_vS32_b_pred_ai_128B<0b11000>; -class V6_vS32b_nt_npred_ai_128B_enc : Enc_COPROC_VMEM_vS32_b_pred_ai_128B<0b11001>; - -class Enc_COPROC_VMEM_vS32b_n_ew_pred_ai opc> : OpcodeHexagon { - bits<2> src1; - bits<5> src2; - bits<10> src3; - bits<4> src3_vector; - bits<3> src4; - - let src3_vector = src3{9-6}; - let Inst{31-16} = { 0b001010001, opc{3}, 1, src2{4-0} }; - let Inst{13-0} = { src3_vector{3}, src1{1-0}, src3_vector{2-0}, 0b01, opc{2-0}, src4{2-0} }; -} - -class V6_vS32b_new_pred_ai_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_ai<0b0000>; -class V6_vS32b_new_npred_ai_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_ai<0b0101>; -class V6_vS32b_nt_new_pred_ai_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_ai<0b1010>; -class V6_vS32b_nt_new_npred_ai_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_ai<0b1111>; - -class Enc_COPROC_VMEM_vS32b_n_ew_pred_ai_128B opc> : OpcodeHexagon { - bits<2> src1; - bits<5> src2; - bits<11> src3; - bits<4> src3_vector; - bits<3> src4; - - let src3_vector = src3{10-7}; - let Inst{31-16} = { 0b001010001, opc{3}, 1, src2{4-0} }; - let Inst{13-0} = { src3_vector{3}, src1{1-0}, src3_vector{2-0}, 0b01, opc{2-0}, src4{2-0} }; -} - -class V6_vS32b_new_pred_ai_128B_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_ai_128B<0b0000>; -class V6_vS32b_new_npred_ai_128B_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_ai_128B<0b0101>; -class V6_vS32b_nt_new_pred_ai_128B_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_ai_128B<0b1010>; -class V6_vS32b_nt_new_npred_ai_128B_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_ai_128B<0b1111>; - -// TODO: Change script to generate dst, src1, src2 instead of -// dst, dst2, src1. -class Enc_COPROC_VMEM_vL32_b_pi opc> : OpcodeHexagon { - bits<5> dst; - bits<5> src1; - bits<9> src2; - bits<3> src2_vector; - - let src2_vector = src2{8-6}; - let Inst{31-16} = { 0b001010010, opc{3}, 0, src1{4-0} }; - let Inst{13-0} = { 0b000, src2_vector{2-0}, opc{2-0}, dst{4-0} }; -} - -class V6_vL32b_pi_enc : Enc_COPROC_VMEM_vL32_b_pi<0b0000>; -class V6_vL32b_cur_pi_enc : Enc_COPROC_VMEM_vL32_b_pi<0b0001>; -class V6_vL32b_tmp_pi_enc : Enc_COPROC_VMEM_vL32_b_pi<0b0010>; -class V6_vL32Ub_pi_enc : Enc_COPROC_VMEM_vL32_b_pi<0b0111>; -class V6_vL32b_nt_pi_enc : Enc_COPROC_VMEM_vL32_b_pi<0b1000>; -class V6_vL32b_nt_cur_pi_enc : Enc_COPROC_VMEM_vL32_b_pi<0b1001>; -class V6_vL32b_nt_tmp_pi_enc : Enc_COPROC_VMEM_vL32_b_pi<0b1010>; - -class Enc_COPROC_VMEM_vL32_b_pi_128B opc> : OpcodeHexagon { - bits<5> dst; - bits<5> src1; - bits<10> src2; - bits<3> src2_vector; - - let src2_vector = src2{9-7}; - let Inst{31-16} = { 0b001010010, opc{3}, 0, src1{4-0} }; - let Inst{13-0} = { 0b000, src2_vector{2-0}, opc{2-0}, dst{4-0} }; -} - -class V6_vL32b_pi_128B_enc : Enc_COPROC_VMEM_vL32_b_pi_128B<0b0000>; -class V6_vL32b_cur_pi_128B_enc : Enc_COPROC_VMEM_vL32_b_pi_128B<0b0001>; -class V6_vL32b_tmp_pi_128B_enc : Enc_COPROC_VMEM_vL32_b_pi_128B<0b0010>; -class V6_vL32Ub_pi_128B_enc : Enc_COPROC_VMEM_vL32_b_pi_128B<0b0111>; -class V6_vL32b_nt_pi_128B_enc : Enc_COPROC_VMEM_vL32_b_pi_128B<0b1000>; -class V6_vL32b_nt_cur_pi_128B_enc : Enc_COPROC_VMEM_vL32_b_pi_128B<0b1001>; -class V6_vL32b_nt_tmp_pi_128B_enc : Enc_COPROC_VMEM_vL32_b_pi_128B<0b1010>; - - -// TODO: Change script to generate src1, src2 and src3 instead of -// dst, src1, src2. -class Enc_COPROC_VMEM_vS32_b_pi opc> : OpcodeHexagon { - bits<5> src1; - bits<9> src2; - bits<3> src2_vector; - bits<5> src3; - - let src2_vector = src2{8-6}; - let Inst{31-16} = { 0b001010010, opc{3}, 1, src1{4-0} }; - let Inst{10-0} = {src2_vector{2-0}, opc{2-0}, src3{4-0} }; -} - -class V6_vS32b_pi_enc : Enc_COPROC_VMEM_vS32_b_pi<0b0000>; -class V6_vS32Ub_pi_enc : Enc_COPROC_VMEM_vS32_b_pi<0b0111>; -class V6_vS32b_nt_pi_enc : Enc_COPROC_VMEM_vS32_b_pi<0b1000>; - -class Enc_COPROC_VMEM_vS32_b_pi_128B opc> : OpcodeHexagon { - bits<5> src1; - bits<10> src2; - bits<3> src2_vector; - bits<5> src3; - - let src2_vector = src2{9-7}; - let Inst{31-16} = { 0b001010010, opc{3}, 1, src1{4-0} }; - let Inst{10-0} = {src2_vector{2-0}, opc{2-0}, src3{4-0} }; -} - -class V6_vS32b_pi_128B_enc : Enc_COPROC_VMEM_vS32_b_pi_128B<0b0000>; -class V6_vS32Ub_pi_128B_enc : Enc_COPROC_VMEM_vS32_b_pi_128B<0b0111>; -class V6_vS32b_nt_pi_128B_enc : Enc_COPROC_VMEM_vS32_b_pi_128B<0b1000>; - -// TODO: Change script to generate src1, src2 and src3 instead of -// dst, src1, src2. -class Enc_COPROC_VMEM_vS32b_n_ew_pi opc> : OpcodeHexagon { - bits<5> src1; - bits<9> src2; - bits<3> src2_vector; - bits<3> src3; - - let src2_vector = src2{8-6}; - let Inst{31-16} = { 0b001010010, opc{0}, 1, src1{4-0} }; - let Inst{13-0} = { 0b000, src2_vector{2-0}, 0b00100, src3{2-0} }; -} - -class V6_vS32b_new_pi_enc : Enc_COPROC_VMEM_vS32b_n_ew_pi<0>; -class V6_vS32b_nt_new_pi_enc : Enc_COPROC_VMEM_vS32b_n_ew_pi<1>; - -class Enc_COPROC_VMEM_vS32b_n_ew_pi_128B opc> : OpcodeHexagon { - bits<5> src1; - bits<10> src2; - bits<3> src2_vector; - bits<3> src3; - - let src2_vector = src2{9-7}; - let Inst{31-16} = { 0b001010010, opc{0}, 1, src1{4-0} }; - let Inst{13-0} = { 0b000, src2_vector{2-0}, 0b00100, src3{2-0} }; -} - -class V6_vS32b_new_pi_128B_enc : Enc_COPROC_VMEM_vS32b_n_ew_pi_128B<0>; -class V6_vS32b_nt_new_pi_128B_enc : Enc_COPROC_VMEM_vS32b_n_ew_pi_128B<1>; - -// TODO: Change script to generate src1, src2,src3 and src4 instead of -// dst, src1, src2, src3. -class Enc_COPROC_VMEM_vS32_b_pred_pi opc> : OpcodeHexagon { - bits<2> src1; - bits<5> src2; - bits<9> src3; - bits<3> src3_vector; - bits<5> src4; - - let src3_vector = src3{8-6}; - let Inst{31-16} = { 0b001010011, opc{4-3}, src2{4-0} }; - let Inst{13-0} = { 0, src1{1-0}, src3_vector{2-0}, opc{2-0}, src4{4-0} }; -} - -class V6_vS32b_qpred_pi_enc : Enc_COPROC_VMEM_vS32_b_pred_pi<0b00000>; -class V6_vS32b_nqpred_pi_enc : Enc_COPROC_VMEM_vS32_b_pred_pi<0b00001>; -class V6_vS32b_pred_pi_enc : Enc_COPROC_VMEM_vS32_b_pred_pi<0b01000>; -class V6_vS32b_npred_pi_enc : Enc_COPROC_VMEM_vS32_b_pred_pi<0b01001>; -class V6_vS32Ub_pred_pi_enc : Enc_COPROC_VMEM_vS32_b_pred_pi<0b01110>; -class V6_vS32Ub_npred_pi_enc : Enc_COPROC_VMEM_vS32_b_pred_pi<0b01111>; -class V6_vS32b_nt_qpred_pi_enc : Enc_COPROC_VMEM_vS32_b_pred_pi<0b10000>; -class V6_vS32b_nt_nqpred_pi_enc : Enc_COPROC_VMEM_vS32_b_pred_pi<0b10001>; -class V6_vS32b_nt_pred_pi_enc : Enc_COPROC_VMEM_vS32_b_pred_pi<0b11000>; -class V6_vS32b_nt_npred_pi_enc : Enc_COPROC_VMEM_vS32_b_pred_pi<0b11001>; - -// TODO: Change script to generate src1, src2,src3 and src4 instead of -// dst, src1, src2, src3. -class Enc_COPROC_VMEM_vS32_b_pred_pi_128B opc> : OpcodeHexagon { - bits<2> src1; - bits<5> src2; - bits<10> src3; - bits<3> src3_vector; - bits<5> src4; - - let src3_vector = src3{9-7}; - let Inst{31-16} = { 0b001010011, opc{4-3}, src2{4-0} }; - let Inst{13-0} = { 0, src1{1-0}, src3_vector{2-0}, opc{2-0}, src4{4-0} }; -} - -class V6_vS32b_qpred_pi_128B_enc : Enc_COPROC_VMEM_vS32_b_pred_pi_128B<0b00000>; -class V6_vS32b_nqpred_pi_128B_enc : Enc_COPROC_VMEM_vS32_b_pred_pi_128B<0b00001>; -class V6_vS32b_pred_pi_128B_enc : Enc_COPROC_VMEM_vS32_b_pred_pi_128B<0b01000>; -class V6_vS32b_npred_pi_128B_enc : Enc_COPROC_VMEM_vS32_b_pred_pi_128B<0b01001>; -class V6_vS32Ub_pred_pi_128B_enc : Enc_COPROC_VMEM_vS32_b_pred_pi_128B<0b01110>; -class V6_vS32Ub_npred_pi_128B_enc : Enc_COPROC_VMEM_vS32_b_pred_pi_128B<0b01111>; -class V6_vS32b_nt_qpred_pi_128B_enc : Enc_COPROC_VMEM_vS32_b_pred_pi_128B<0b10000>; -class V6_vS32b_nt_nqpred_pi_128B_enc : Enc_COPROC_VMEM_vS32_b_pred_pi_128B<0b10001>; -class V6_vS32b_nt_pred_pi_128B_enc : Enc_COPROC_VMEM_vS32_b_pred_pi_128B<0b11000>; -class V6_vS32b_nt_npred_pi_128B_enc : Enc_COPROC_VMEM_vS32_b_pred_pi_128B<0b11001>; - -class Enc_COPROC_VMEM_vS32b_n_ew_pred_pi opc> : OpcodeHexagon { - bits<2> src1; - bits<5> src2; - bits<9> src3; - bits<3> src3_vector; - bits<3> src4; - - let src3_vector = src3{8-6}; - let Inst{31-16} = { 0b001010011, opc{3}, 1, src2{4-0} }; - let Inst{13-0} = { 0, src1{1-0}, src3_vector{2-0}, 0b01, opc{2-0}, src4{2-0} }; -} - -class V6_vS32b_new_pred_pi_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_pi<0b0000>; -class V6_vS32b_new_npred_pi_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_pi<0b0101>; -class V6_vS32b_nt_new_pred_pi_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_pi<0b1010>; -class V6_vS32b_nt_new_npred_pi_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_pi<0b1111>; - -class Enc_COPROC_VMEM_vS32b_n_ew_pred_pi_128B opc> : OpcodeHexagon { - bits<2> src1; - bits<5> src2; - bits<10> src3; - bits<3> src3_vector; - bits<3> src4; - - let src3_vector = src3{9-7}; - let Inst{31-16} = { 0b001010011, opc{3}, 1, src2{4-0} }; - let Inst{13-0} = { 0, src1{1-0}, src3_vector{2-0}, 0b01, opc{2-0}, src4{2-0} }; -} - -class V6_vS32b_new_pred_pi_128B_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_pi_128B<0b0000>; -class V6_vS32b_new_npred_pi_128B_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_pi_128B<0b0101>; -class V6_vS32b_nt_new_pred_pi_128B_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_pi_128B<0b1010>; -class V6_vS32b_nt_new_npred_pi_128B_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_pi_128B<0b1111>; - -class Enc_LD_load_m opc> : OpcodeHexagon { - bits<5> dst; - bits<5> src1; - bits<1> src2; - - let Inst{31-16} = { opc{12}, 0, opc{11-10}, 1, opc{9-4}, src1{4-0} }; - let Inst{13-0} = { src2{0}, 0b000, opc{3}, 0, opc{2-0}, dst{4-0} }; -} - -class V6_vL32b_ppu_enc : Enc_LD_load_m<0b0100110000000>; -class V6_vL32b_cur_ppu_enc : Enc_LD_load_m<0b0100110000001>; -class V6_vL32b_tmp_ppu_enc : Enc_LD_load_m<0b0100110000010>; -class V6_vL32Ub_ppu_enc : Enc_LD_load_m<0b0100110000111>; -class V6_vL32b_nt_ppu_enc : Enc_LD_load_m<0b0100110100000>; -class V6_vL32b_nt_cur_ppu_enc : Enc_LD_load_m<0b0100110100001>; -class V6_vL32b_nt_tmp_ppu_enc : Enc_LD_load_m<0b0100110100010>; - -class Enc_COPROC_VMEM_vS32_b_ppu opc> : OpcodeHexagon { - bits<5> src1; - bits<1> src2; - bits<5> src3; - - let Inst{31-16} = { 0b001010110, opc{3}, 1, src1{4-0} }; - let Inst{13-0} = { src2{0}, 0b00000, opc{2-0}, src3{4-0} }; -} - -class V6_vS32b_ppu_enc : Enc_COPROC_VMEM_vS32_b_ppu<0b0000>; -class V6_vS32Ub_ppu_enc : Enc_COPROC_VMEM_vS32_b_ppu<0b0111>; -class V6_vS32b_nt_ppu_enc : Enc_COPROC_VMEM_vS32_b_ppu<0b1000>; - -class Enc_COPROC_VMEM_vS32b_new_ppu opc> : OpcodeHexagon { - bits<5> src1; - bits<1> src2; - bits<3> src3; - - let Inst{31-16} = { 0b001010110, opc{0}, 1, src1{4-0} }; - let Inst{13-0} = { src2{0}, 0b0000000100, src3{2-0} }; -} - -class V6_vS32b_new_ppu_enc : Enc_COPROC_VMEM_vS32b_new_ppu<0>; -class V6_vS32b_nt_new_ppu_enc : Enc_COPROC_VMEM_vS32b_new_ppu<1>; - -class Enc_COPROC_VMEM_vS32_b_pred_ppu opc> : OpcodeHexagon { - bits<2> src1; - bits<5> src2; - bits<1> src3; - bits<5> src4; - - let Inst{31-16} = { 0b001010111, opc{4-3}, src2{4-0} }; - let Inst{13-0} = { src3{0}, src1{1-0}, 0b000, opc{2-0}, src4{4-0} }; -} - -class V6_vS32b_qpred_ppu_enc : Enc_COPROC_VMEM_vS32_b_pred_ppu<0b00000>; -class V6_vS32b_nqpred_ppu_enc : Enc_COPROC_VMEM_vS32_b_pred_ppu<0b00001>; -class V6_vS32b_pred_ppu_enc : Enc_COPROC_VMEM_vS32_b_pred_ppu<0b01000>; -class V6_vS32b_npred_ppu_enc : Enc_COPROC_VMEM_vS32_b_pred_ppu<0b01001>; -class V6_vS32Ub_pred_ppu_enc : Enc_COPROC_VMEM_vS32_b_pred_ppu<0b01110>; -class V6_vS32Ub_npred_ppu_enc : Enc_COPROC_VMEM_vS32_b_pred_ppu<0b01111>; -class V6_vS32b_nt_qpred_ppu_enc : Enc_COPROC_VMEM_vS32_b_pred_ppu<0b10000>; -class V6_vS32b_nt_nqpred_ppu_enc : Enc_COPROC_VMEM_vS32_b_pred_ppu<0b10001>; -class V6_vS32b_nt_pred_ppu_enc : Enc_COPROC_VMEM_vS32_b_pred_ppu<0b11000>; -class V6_vS32b_nt_npred_ppu_enc : Enc_COPROC_VMEM_vS32_b_pred_ppu<0b11001>; - -class Enc_COPROC_VMEM_vS32b_n_ew_pred_ppu opc> : OpcodeHexagon { - bits<2> src1; - bits<5> src2; - bits<1> src3; - bits<3> src4; - - let Inst{31-16} = { 0b001010111, opc{3}, 1, src2{4-0} }; - let Inst{13-0} = { src3{0}, src1{1-0}, 0b00001, opc{2-0}, src4{2-0} }; -} - -class V6_vS32b_new_pred_ppu_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_ppu<0b0000>; -class V6_vS32b_new_npred_ppu_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_ppu<0b0101>; -class V6_vS32b_nt_new_pred_ppu_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_ppu<0b1010>; -class V6_vS32b_nt_new_npred_ppu_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_ppu<0b1111>; - - -class Enc_COPROC_VX_4op_i opc> : OpcodeHexagon { - bits<5> dst; - bits<5> src1; - bits<5> src2; - bits<1> src3; - - let Inst{31-16} = { 0b00011001, opc{4-2}, src2{4-0} }; - let Inst{13-0} = { opc{1}, src1{4-0}, 1, opc{0}, src3{0}, dst{4-0} }; -} - -class V6_vrmpybusi_enc : Enc_COPROC_VX_4op_i<0b01000>; -class V6_vrsadubi_enc : Enc_COPROC_VX_4op_i<0b01001>; -class V6_vrmpybusi_acc_enc : Enc_COPROC_VX_4op_i<0b01010>; -class V6_vrsadubi_acc_enc : Enc_COPROC_VX_4op_i<0b01011>; -class V6_vrmpyubi_acc_enc : Enc_COPROC_VX_4op_i<0b01111>; -class V6_vrmpyubi_enc : Enc_COPROC_VX_4op_i<0b10101>; - -class Enc_COPROC_VX_vandqrt opc> : OpcodeHexagon { - bits<5> dst; - bits<2> src1; - bits<5> src2; - - let Inst{31-16} = { 0b00011001, opc{4-3}, 1, src2{4-0} }; - let Inst{13-0} = { opc{2}, 0b000, src1{1-0}, opc{1-0}, 1, dst{4-0} }; -} - -class V6_vandqrt_acc_enc : Enc_COPROC_VX_vandqrt<0b01101>; -class V6_vandqrt_enc : Enc_COPROC_VX_vandqrt<0b10010>; - -class Enc_COPROC_VX_cards opc> : OpcodeHexagon { - bits<5> src1; - bits<5> src2; - bits<5> src3; - - let Inst{31-16} = { 0b00011001111, src3{4-0} }; - let Inst{13-0} = { 1, src1{4-0}, 0, opc{1-0}, src2{4-0} }; -} - -class V6_vshuff_enc : Enc_COPROC_VX_cards<0b01>; -class V6_vdeal_enc : Enc_COPROC_VX_cards<0b10>; - - -class Enc_COPROC_VX_v_cmov opc> : OpcodeHexagon { - bits<2> src1; - bits<5> dst; - bits<5> src2; - - let Inst{31-16} = { 0b0001101000, opc{0}, 0b00000 }; - let Inst{13-0} = { 0, src2{4-0}, 0, src1{1-0}, dst{4-0} }; -} - -class V6_vcmov_enc : Enc_COPROC_VX_v_cmov<0>; -class V6_vncmov_enc : Enc_COPROC_VX_v_cmov<1>; - -class Enc_X_p3op opc> : OpcodeHexagon { - bits<2> src1; - bits<5> dst; - bits<5> src2; - bits<5> src3; - - let Inst{31-16} = { opc{7-5}, 0b1101, opc{4}, 0, opc{3-2}, src3{4-0} }; - let Inst{13-0} = { opc{1}, src2{4-0}, opc{0}, src1{1-0}, dst{4-0} }; -} - -class V6_vnccombine_enc : Enc_X_p3op<0b00001000>; -class V6_vccombine_enc : Enc_X_p3op<0b00001100>; - -class Enc_COPROC_VX_4op_r opc> : OpcodeHexagon { - bits<5> dst; - bits<5> src1; - bits<5> src2; - bits<3> src3; - - let Inst{31-16} = { 0b00011011, src2{4-0}, src3{2-0} }; - let Inst{13-0} = { opc{3}, src1{4-0}, opc{2-0}, dst{4-0} }; -} - -class V6_valignb_enc : Enc_COPROC_VX_4op_r<0b0000>; -class V6_vlalignb_enc : Enc_COPROC_VX_4op_r<0b0001>; -class V6_vasrwh_enc : Enc_COPROC_VX_4op_r<0b0010>; -class V6_vasrwhsat_enc : Enc_COPROC_VX_4op_r<0b0011>; -class V6_vasrwhrndsat_enc : Enc_COPROC_VX_4op_r<0b0100>; -class V6_vasrwuhsat_enc : Enc_COPROC_VX_4op_r<0b0101>; -class V6_vasrhubsat_enc : Enc_COPROC_VX_4op_r<0b0110>; -class V6_vasrhubrndsat_enc : Enc_COPROC_VX_4op_r<0b0111>; -class V6_vasrhbrndsat_enc : Enc_COPROC_VX_4op_r<0b1000>; -class V6_vlutvvb_enc : Enc_COPROC_VX_4op_r<0b1001>; -class V6_vshuffvdd_enc : Enc_COPROC_VX_4op_r<0b1011>; -class V6_vdealvdd_enc : Enc_COPROC_VX_4op_r<0b1100>; -class V6_vlutvvb_oracc_enc : Enc_COPROC_VX_4op_r<0b1101>; -class V6_vlutvwh_enc : Enc_COPROC_VX_4op_r<0b1110>; -class V6_vlutvwh_oracc_enc : Enc_COPROC_VX_4op_r<0b1111>; - -class Enc_S_3op_valign_i opc> : OpcodeHexagon { - bits<5> dst; - bits<5> src1; - bits<5> src2; - bits<3> src3; - - let Inst{31-16} = { opc{8-7}, 0, opc{6-3}, 0b00, opc{2-1}, src2{4-0} }; - let Inst{13-0} = { opc{0}, src1{4-0}, src3{2-0}, dst{4-0} }; -} - -class V6_vlutb_enc : Enc_S_3op_valign_i<0b001100000>; -class V6_vlutb_dv_enc : Enc_S_3op_valign_i<0b001100010>; -class V6_vlutb_acc_enc : Enc_S_3op_valign_i<0b001100100>; -class V6_vlutb_dv_acc_enc : Enc_S_3op_valign_i<0b001100110>; -class V6_valignbi_enc : Enc_S_3op_valign_i<0b001111011>; -class V6_vlalignbi_enc : Enc_S_3op_valign_i<0b001111111>; -class S2_valignib_enc : Enc_S_3op_valign_i<0b110000000>; -class S2_addasl_rrri_enc : Enc_S_3op_valign_i<0b110010000>; - -class Enc_COPROC_VX_3op_q opc> : OpcodeHexagon { - bits<2> dst; - bits<2> src1; - bits<2> src2; - - let Inst{31-16} = { 0b00011110, src2{1-0}, 0b000011 }; - let Inst{13-0} = { 0b0000, src1{1-0}, 0b000, opc{2-0}, dst{1-0} }; -} - -class V6_pred_and_enc : Enc_COPROC_VX_3op_q<0b000>; -class V6_pred_or_enc : Enc_COPROC_VX_3op_q<0b001>; -class V6_pred_xor_enc : Enc_COPROC_VX_3op_q<0b011>; -class V6_pred_or_n_enc : Enc_COPROC_VX_3op_q<0b100>; -class V6_pred_and_n_enc : Enc_COPROC_VX_3op_q<0b101>; - -class V6_pred_not_enc : OpcodeHexagon { - bits<2> dst; - bits<2> src1; - - let Inst{31-16} = { 0b0001111000000011 }; - let Inst{13-0} = { 0b0000, src1{1-0}, 0b000010, dst{1-0} }; -} - -class Enc_COPROC_VX_4op_q opc> : OpcodeHexagon { - bits<5> dst; - bits<2> src1; - bits<5> src2; - bits<5> src3; - - let Inst{31-16} = { 0b000111101, opc{0}, 1, src3{4-0} }; - let Inst{13-0} = { 1, src2{4-0}, 0, src1{1-0}, dst{4-0} }; -} - -class V6_vswap_enc : Enc_COPROC_VX_4op_q<0>; -class V6_vmux_enc : Enc_COPROC_VX_4op_q<1>; - -class Enc_X_2op opc> : OpcodeHexagon { - bits<5> dst; - bits<5> src1; - - let Inst{31-16} = { opc{15-5}, src1{4-0} }; - let Inst{13-0} = { opc{4-3}, 0b0000, opc{2-0}, dst{4-0} }; -} - -class V6_lvsplatw_enc : Enc_X_2op<0b0001100110100001>; -class V6_vinsertwr_enc : Enc_X_2op<0b0001100110110001>; -class S6_vsplatrbp_enc : Enc_X_2op<0b1000010001000100>; - - -class Enc_CR_2op_r opc> : OpcodeHexagon { - bits<2> dst; - bits<5> src1; - - let Inst{31-16} = { opc{11}, 0, opc{10-7}, 0, opc{6-3}, src1{4-0} }; - let Inst{13-0} = { opc{2}, 0b000000, opc{1}, 0b000, opc{0}, dst{1-0} }; -} - -class V6_pred_scalar2_enc : Enc_CR_2op_r<0b001101101011>; -class Y5_l2locka_enc : Enc_CR_2op_r<0b110000111100>; - -class Enc_S_3op_i6 opc> : OpcodeHexagon { - bits<5> dst; - bits<5> src1; - bits<6> src2; - - let Inst{31-16} = { 0b1000, opc{8-6}, 0, opc{5-3}, src1{4-0} }; - let Inst{13-0} = { src2{5-0}, opc{2-0}, dst{4-0} }; -} - -class S6_rol_i_p_enc : Enc_S_3op_i6<0b000000011>; -class S6_rol_i_p_nac_enc : Enc_S_3op_i6<0b001000011>; -class S6_rol_i_p_acc_enc : Enc_S_3op_i6<0b001000111>; -class S6_rol_i_p_and_enc : Enc_S_3op_i6<0b001010011>; -class S6_rol_i_p_or_enc : Enc_S_3op_i6<0b001010111>; -class S6_rol_i_p_xacc_enc : Enc_S_3op_i6<0b001100011>; - -class Enc_X_3op_r opc> : OpcodeHexagon { - bits<5> dst; - bits<5> src1; - bits<5> src2; - - let Inst{31-16} = { opc{14-4}, src1{4-0} }; - let Inst{13-0} = { opc{3}, src2{4-0}, opc{2-0}, dst{4-0} }; -} - -class S6_rol_i_r_enc : Enc_X_3op_r<0b100011000000011>; -class S6_rol_i_r_nac_enc : Enc_X_3op_r<0b100011100000011>; -class S6_rol_i_r_acc_enc : Enc_X_3op_r<0b100011100000111>; -class S6_rol_i_r_and_enc : Enc_X_3op_r<0b100011100100011>; -class S6_rol_i_r_or_enc : Enc_X_3op_r<0b100011100100111>; -class S6_rol_i_r_xacc_enc : Enc_X_3op_r<0b100011101000011>; -class S6_vtrunehb_ppp_enc : Enc_X_3op_r<0b110000011000011>; -class S6_vtrunohb_ppp_enc : Enc_X_3op_r<0b110000011000101>; - -class Enc_no_operands opc> : OpcodeHexagon { - - let Inst{31-16} = { opc{24-10}, 0 }; - let Inst{13-0} = { opc{9-7}, 0b000, opc{6-0}, 0 }; -} - -class Y5_l2gunlock_enc : Enc_no_operands<0b1010100000100000010000000>; -class Y5_l2gclean_enc : Enc_no_operands<0b1010100000100000100000000>; -class Y5_l2gcleaninv_enc : Enc_no_operands<0b1010100000100000110000000>; -class V6_vhist_enc : Enc_no_operands<0b0001111000000001001000000>; - -class Enc_J_jumpr opc> : OpcodeHexagon { - bits<5> src1; - - let Inst{31-16} = { opc{12-6}, 0, opc{5-3}, src1{4-0} }; - let Inst{13-0} = { 0b00, opc{2}, 0b0000, opc{1-0}, 0b00000 }; -} - -class Y5_l2unlocka_enc : Enc_J_jumpr<0b1010011011000>; -class Y2_l2cleaninvidx_enc : Enc_J_jumpr<0b1010100011000>; - -class Enc_ST_l2gclean_pa opc> : OpcodeHexagon { - bits<5> src1; - - let Inst{31-16} = { 0b101001101, opc{1-0}, 0b00000 }; - let Inst{13-0} = { 0, src1{4-0}, 0b00000000 }; -} - -class Y6_l2gcleanpa_enc : Enc_ST_l2gclean_pa<0b01>; -class Y6_l2gcleaninvpa_enc : Enc_ST_l2gclean_pa<0b10>; - -class A5_ACS_enc : OpcodeHexagon { - bits<5> dst1; - bits<2> dst2; - bits<5> src1; - bits<5> src2; - - let Inst{31-16} = { 0b11101010101, src1{4-0} }; - let Inst{13-0} = { 0, src2{4-0}, 0, dst2{1-0}, dst1{4-0} }; -} - -class Enc_X_4op_r opc> : OpcodeHexagon { - bits<5> dst; - bits<5> src1; - bits<5> src2; - bits<2> src3; - - let Inst{31-16} = { 0b11, opc{7}, 0, opc{6-5}, 1, opc{4-1}, src1{4-0} }; - let Inst{13-0} = { 0, src2{4-0}, opc{0}, src3{1-0}, dst{4-0} }; -} - -class S2_vsplicerb_enc : Enc_X_4op_r<0b00001000>; -class S2_cabacencbin_enc : Enc_X_4op_r<0b00001010>; -class F2_sffma_sc_enc : Enc_X_4op_r<0b11110111>; - -class V6_vhistq_enc : OpcodeHexagon { - bits<2> src1; - - let Inst{31-16} = { 0b00011110, src1{1-0}, 0b000010 }; - let Inst{13-0} = { 0b10000010000000 }; -} - -// TODO: Change script to generate dst1 instead of dst. -class A6_vminub_RdP_enc : OpcodeHexagon { - bits<5> dst1; - bits<2> dst2; - bits<5> src1; - bits<5> src2; - - let Inst{31-16} = { 0b11101010111, src2{4-0} }; - let Inst{13-0} = { 0, src1{4-0}, 0, dst2{1-0}, dst1{4-0} }; -} diff --git a/lib/Target/Hexagon/HexagonIsetDx.td b/lib/Target/Hexagon/HexagonIsetDx.td deleted file mode 100644 index ebedf2cbaf1..00000000000 --- a/lib/Target/Hexagon/HexagonIsetDx.td +++ /dev/null @@ -1,728 +0,0 @@ -//=- HexagonIsetDx.td - Target Desc. for Hexagon Target -*- tablegen -*-=// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file describes the Hexagon duplex instructions. -// -//===----------------------------------------------------------------------===// - -// SA1_combine1i: Combines. -let isCodeGenOnly = 1, hasSideEffects = 0 in -def SA1_combine1i: SUBInst < - (outs DoubleRegs:$Rdd), - (ins u2_0Imm:$u2), - "$Rdd = combine(#1, #$u2)"> { - bits<3> Rdd; - bits<2> u2; - - let Inst{12-10} = 0b111; - let Inst{8} = 0b0; - let Inst{4-3} = 0b01; - let Inst{2-0} = Rdd; - let Inst{6-5} = u2; - } - -// SL2_jumpr31_f: Indirect conditional jump if false. -// SL2_jumpr31_f -> SL2_jumpr31_fnew -let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in -def SL2_jumpr31_f: SUBInst < - (outs ), - (ins ), - "if (!p0) jumpr r31"> { - let Inst{12-6} = 0b1111111; - let Inst{2-0} = 0b101; - } - -// SL2_deallocframe: Deallocate stack frame. -let Defs = [R31, R29, R30], Uses = [R30], isCodeGenOnly = 1, mayLoad = 1, accessSize = DoubleWordAccess in -def SL2_deallocframe: SUBInst < - (outs ), - (ins ), - "deallocframe"> { - let Inst{12-6} = 0b1111100; - let Inst{2} = 0b0; - } - -// SL2_return_f: Deallocate stack frame and return. -// SL2_return_f -> SL2_return_fnew -let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, mayLoad = 1, accessSize = DoubleWordAccess, isBranch = 1, isIndirectBranch = 1 in -def SL2_return_f: SUBInst < - (outs ), - (ins ), - "if (!p0) dealloc_return"> { - let Inst{12-6} = 0b1111101; - let Inst{2-0} = 0b101; - } - -// SA1_combine3i: Combines. -let isCodeGenOnly = 1, hasSideEffects = 0 in -def SA1_combine3i: SUBInst < - (outs DoubleRegs:$Rdd), - (ins u2_0Imm:$u2), - "$Rdd = combine(#3, #$u2)"> { - bits<3> Rdd; - bits<2> u2; - - let Inst{12-10} = 0b111; - let Inst{8} = 0b0; - let Inst{4-3} = 0b11; - let Inst{2-0} = Rdd; - let Inst{6-5} = u2; - } - -// SS2_storebi0: Store byte. -let isCodeGenOnly = 1, mayStore = 1, accessSize = ByteAccess in -def SS2_storebi0: SUBInst < - (outs ), - (ins IntRegs:$Rs, u4_0Imm:$u4_0), - "memb($Rs + #$u4_0)=#0"> { - bits<4> Rs; - bits<4> u4_0; - - let Inst{12-8} = 0b10010; - let Inst{7-4} = Rs; - let Inst{3-0} = u4_0; - } - -// SA1_clrtnew: Clear if true. -let Uses = [P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedNew = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -def SA1_clrtnew: SUBInst < - (outs IntRegs:$Rd), - (ins PredRegs:$Pu), - "if ($Pu.new) $Rd = #0"> { - bits<4> Rd; - - let Inst{12-9} = 0b1101; - let Inst{6-4} = 0b100; - let Inst{3-0} = Rd; - } - -// SL2_loadruh_io: Load half. -let isCodeGenOnly = 1, mayLoad = 1, accessSize = HalfWordAccess, hasNewValue = 1, opNewValue = 0 in -def SL2_loadruh_io: SUBInst < - (outs IntRegs:$Rd), - (ins IntRegs:$Rs, u3_1Imm:$u3_1), - "$Rd = memuh($Rs + #$u3_1)"> { - bits<4> Rd; - bits<4> Rs; - bits<4> u3_1; - - let Inst{12-11} = 0b01; - let Inst{3-0} = Rd; - let Inst{7-4} = Rs; - let Inst{10-8} = u3_1{3-1}; - } - -// SL2_jumpr31_tnew: Indirect conditional jump if true. -let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isPredicatedNew = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in -def SL2_jumpr31_tnew: SUBInst < - (outs ), - (ins ), - "if (p0.new) jumpr:nt r31"> { - let Inst{12-6} = 0b1111111; - let Inst{2-0} = 0b110; - } - -// SA1_addi: Add. -let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0, isExtendable = 1, isExtentSigned = 1, opExtentBits = 7, opExtendable = 2 in -def SA1_addi: SUBInst < - (outs IntRegs:$Rx), - (ins IntRegs:$_src_, s7_0Ext:$s7), - "$Rx = add($_src_, #$s7)" , - [] , - "$_src_ = $Rx"> { - bits<4> Rx; - bits<7> s7; - - let Inst{12-11} = 0b00; - let Inst{3-0} = Rx; - let Inst{10-4} = s7; - } - -// SL1_loadrub_io: Load byte. -let isCodeGenOnly = 1, mayLoad = 1, accessSize = ByteAccess, hasNewValue = 1, opNewValue = 0 in -def SL1_loadrub_io: SUBInst < - (outs IntRegs:$Rd), - (ins IntRegs:$Rs, u4_0Imm:$u4_0), - "$Rd = memub($Rs + #$u4_0)"> { - bits<4> Rd; - bits<4> Rs; - bits<4> u4_0; - - let Inst{12} = 0b1; - let Inst{3-0} = Rd; - let Inst{7-4} = Rs; - let Inst{11-8} = u4_0; - } - -// SL1_loadri_io: Load word. -let isCodeGenOnly = 1, mayLoad = 1, accessSize = WordAccess, hasNewValue = 1, opNewValue = 0 in -def SL1_loadri_io: SUBInst < - (outs IntRegs:$Rd), - (ins IntRegs:$Rs, u4_2Imm:$u4_2), - "$Rd = memw($Rs + #$u4_2)"> { - bits<4> Rd; - bits<4> Rs; - bits<6> u4_2; - - let Inst{12} = 0b0; - let Inst{3-0} = Rd; - let Inst{7-4} = Rs; - let Inst{11-8} = u4_2{5-2}; - } - -// SA1_cmpeqi: Compareimmed. -let Defs = [P0], isCodeGenOnly = 1, hasSideEffects = 0 in -def SA1_cmpeqi: SUBInst < - (outs ), - (ins IntRegs:$Rs, u2_0Imm:$u2), - "p0 = cmp.eq($Rs, #$u2)"> { - bits<4> Rs; - bits<2> u2; - - let Inst{12-8} = 0b11001; - let Inst{7-4} = Rs; - let Inst{1-0} = u2; - } - -// SA1_combinerz: Combines. -let isCodeGenOnly = 1, hasSideEffects = 0 in -def SA1_combinerz: SUBInst < - (outs DoubleRegs:$Rdd), - (ins IntRegs:$Rs), - "$Rdd = combine($Rs, #0)"> { - bits<3> Rdd; - bits<4> Rs; - - let Inst{12-10} = 0b111; - let Inst{8} = 0b1; - let Inst{3} = 0b1; - let Inst{2-0} = Rdd; - let Inst{7-4} = Rs; - } - -// SL2_return_t: Deallocate stack frame and return. -// SL2_return_t -> SL2_return_tnew -let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, mayLoad = 1, accessSize = DoubleWordAccess, isBranch = 1, isIndirectBranch = 1 in -def SL2_return_t: SUBInst < - (outs ), - (ins ), - "if (p0) dealloc_return"> { - let Inst{12-6} = 0b1111101; - let Inst{2-0} = 0b100; - } - -// SS2_allocframe: Allocate stack frame. -let Defs = [R29, R30], Uses = [R30, R31, R29], isCodeGenOnly = 1, mayStore = 1, accessSize = DoubleWordAccess in -def SS2_allocframe: SUBInst < - (outs ), - (ins u5_3Imm:$u5_3), - "allocframe(#$u5_3)"> { - bits<8> u5_3; - - let Inst{12-9} = 0b1110; - let Inst{8-4} = u5_3{7-3}; - } - -// SS2_storeh_io: Store half. -let isCodeGenOnly = 1, mayStore = 1, accessSize = HalfWordAccess in -def SS2_storeh_io: SUBInst < - (outs ), - (ins IntRegs:$Rs, u3_1Imm:$u3_1, IntRegs:$Rt), - "memh($Rs + #$u3_1) = $Rt"> { - bits<4> Rs; - bits<4> u3_1; - bits<4> Rt; - - let Inst{12-11} = 0b00; - let Inst{7-4} = Rs; - let Inst{10-8} = u3_1{3-1}; - let Inst{3-0} = Rt; - } - -// SS2_storewi0: Store word. -let isCodeGenOnly = 1, mayStore = 1, accessSize = WordAccess in -def SS2_storewi0: SUBInst < - (outs ), - (ins IntRegs:$Rs, u4_2Imm:$u4_2), - "memw($Rs + #$u4_2)=#0"> { - bits<4> Rs; - bits<6> u4_2; - - let Inst{12-8} = 0b10000; - let Inst{7-4} = Rs; - let Inst{3-0} = u4_2{5-2}; - } - -// SS2_storewi1: Store word. -let isCodeGenOnly = 1, mayStore = 1, accessSize = WordAccess in -def SS2_storewi1: SUBInst < - (outs ), - (ins IntRegs:$Rs, u4_2Imm:$u4_2), - "memw($Rs + #$u4_2)=#1"> { - bits<4> Rs; - bits<6> u4_2; - - let Inst{12-8} = 0b10001; - let Inst{7-4} = Rs; - let Inst{3-0} = u4_2{5-2}; - } - -// SL2_jumpr31: Indirect conditional jump if true. -let Defs = [PC], Uses = [R31], isCodeGenOnly = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in -def SL2_jumpr31: SUBInst < - (outs ), - (ins ), - "jumpr r31"> { - let Inst{12-6} = 0b1111111; - let Inst{2} = 0b0; - } - -// SA1_combinezr: Combines. -let isCodeGenOnly = 1, hasSideEffects = 0 in -def SA1_combinezr: SUBInst < - (outs DoubleRegs:$Rdd), - (ins IntRegs:$Rs), - "$Rdd = combine(#0, $Rs)"> { - bits<3> Rdd; - bits<4> Rs; - - let Inst{12-10} = 0b111; - let Inst{8} = 0b1; - let Inst{3} = 0b0; - let Inst{2-0} = Rdd; - let Inst{7-4} = Rs; - } - -// SL2_loadrh_io: Load half. -let isCodeGenOnly = 1, mayLoad = 1, accessSize = HalfWordAccess, hasNewValue = 1, opNewValue = 0 in -def SL2_loadrh_io: SUBInst < - (outs IntRegs:$Rd), - (ins IntRegs:$Rs, u3_1Imm:$u3_1), - "$Rd = memh($Rs + #$u3_1)"> { - bits<4> Rd; - bits<4> Rs; - bits<4> u3_1; - - let Inst{12-11} = 0b00; - let Inst{3-0} = Rd; - let Inst{7-4} = Rs; - let Inst{10-8} = u3_1{3-1}; - } - -// SA1_addrx: Add. -let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -def SA1_addrx: SUBInst < - (outs IntRegs:$Rx), - (ins IntRegs:$_src_, IntRegs:$Rs), - "$Rx = add($_src_, $Rs)" , - [] , - "$_src_ = $Rx"> { - bits<4> Rx; - bits<4> Rs; - - let Inst{12-8} = 0b11000; - let Inst{3-0} = Rx; - let Inst{7-4} = Rs; - } - -// SA1_setin1: Set to -1. -let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -def SA1_setin1: SUBInst < - (outs IntRegs:$Rd), - (ins ), - "$Rd = #{-1}"> { - bits<4> Rd; - - let Inst{12-9} = 0b1101; - let Inst{6} = 0b0; - let Inst{3-0} = Rd; - } - -// SA1_sxth: Sxth. -let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -def SA1_sxth: SUBInst < - (outs IntRegs:$Rd), - (ins IntRegs:$Rs), - "$Rd = sxth($Rs)"> { - bits<4> Rd; - bits<4> Rs; - - let Inst{12-8} = 0b10100; - let Inst{3-0} = Rd; - let Inst{7-4} = Rs; - } - -// SA1_combine0i: Combines. -let isCodeGenOnly = 1, hasSideEffects = 0 in -def SA1_combine0i: SUBInst < - (outs DoubleRegs:$Rdd), - (ins u2_0Imm:$u2), - "$Rdd = combine(#0, #$u2)"> { - bits<3> Rdd; - bits<2> u2; - - let Inst{12-10} = 0b111; - let Inst{8} = 0b0; - let Inst{4-3} = 0b00; - let Inst{2-0} = Rdd; - let Inst{6-5} = u2; - } - -// SA1_combine2i: Combines. -let isCodeGenOnly = 1, hasSideEffects = 0 in -def SA1_combine2i: SUBInst < - (outs DoubleRegs:$Rdd), - (ins u2_0Imm:$u2), - "$Rdd = combine(#2, #$u2)"> { - bits<3> Rdd; - bits<2> u2; - - let Inst{12-10} = 0b111; - let Inst{8} = 0b0; - let Inst{4-3} = 0b10; - let Inst{2-0} = Rdd; - let Inst{6-5} = u2; - } - -// SA1_sxtb: Sxtb. -let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -def SA1_sxtb: SUBInst < - (outs IntRegs:$Rd), - (ins IntRegs:$Rs), - "$Rd = sxtb($Rs)"> { - bits<4> Rd; - bits<4> Rs; - - let Inst{12-8} = 0b10101; - let Inst{3-0} = Rd; - let Inst{7-4} = Rs; - } - -// SA1_clrf: Clear if false. -// SA1_clrf -> SA1_clrfnew -let Uses = [P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -def SA1_clrf: SUBInst < - (outs IntRegs:$Rd), - (ins PredRegs:$Pu), - "if (!$Pu) $Rd = #0"> { - bits<4> Rd; - - let Inst{12-9} = 0b1101; - let Inst{6-4} = 0b111; - let Inst{3-0} = Rd; - } - -// SL2_loadrb_io: Load byte. -let isCodeGenOnly = 1, mayLoad = 1, accessSize = ByteAccess, hasNewValue = 1, opNewValue = 0 in -def SL2_loadrb_io: SUBInst < - (outs IntRegs:$Rd), - (ins IntRegs:$Rs, u3_0Imm:$u3_0), - "$Rd = memb($Rs + #$u3_0)"> { - bits<4> Rd; - bits<4> Rs; - bits<3> u3_0; - - let Inst{12-11} = 0b10; - let Inst{3-0} = Rd; - let Inst{7-4} = Rs; - let Inst{10-8} = u3_0; - } - -// SA1_tfr: Tfr. -let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -def SA1_tfr: SUBInst < - (outs IntRegs:$Rd), - (ins IntRegs:$Rs), - "$Rd = $Rs"> { - bits<4> Rd; - bits<4> Rs; - - let Inst{12-8} = 0b10000; - let Inst{3-0} = Rd; - let Inst{7-4} = Rs; - } - -// SL2_loadrd_sp: Load dword. -let Uses = [R29], isCodeGenOnly = 1, mayLoad = 1, accessSize = DoubleWordAccess in -def SL2_loadrd_sp: SUBInst < - (outs DoubleRegs:$Rdd), - (ins u5_3Imm:$u5_3), - "$Rdd = memd(r29 + #$u5_3)"> { - bits<3> Rdd; - bits<8> u5_3; - - let Inst{12-8} = 0b11110; - let Inst{2-0} = Rdd; - let Inst{7-3} = u5_3{7-3}; - } - -// SA1_and1: And #1. -let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -def SA1_and1: SUBInst < - (outs IntRegs:$Rd), - (ins IntRegs:$Rs), - "$Rd = and($Rs, #1)"> { - bits<4> Rd; - bits<4> Rs; - - let Inst{12-8} = 0b10010; - let Inst{3-0} = Rd; - let Inst{7-4} = Rs; - } - -// SS2_storebi1: Store byte. -let isCodeGenOnly = 1, mayStore = 1, accessSize = ByteAccess in -def SS2_storebi1: SUBInst < - (outs ), - (ins IntRegs:$Rs, u4_0Imm:$u4_0), - "memb($Rs + #$u4_0)=#1"> { - bits<4> Rs; - bits<4> u4_0; - - let Inst{12-8} = 0b10011; - let Inst{7-4} = Rs; - let Inst{3-0} = u4_0; - } - -// SA1_inc: Inc. -let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -def SA1_inc: SUBInst < - (outs IntRegs:$Rd), - (ins IntRegs:$Rs), - "$Rd = add($Rs, #1)"> { - bits<4> Rd; - bits<4> Rs; - - let Inst{12-8} = 0b10001; - let Inst{3-0} = Rd; - let Inst{7-4} = Rs; - } - -// SS2_stored_sp: Store dword. -let Uses = [R29], isCodeGenOnly = 1, mayStore = 1, accessSize = DoubleWordAccess in -def SS2_stored_sp: SUBInst < - (outs ), - (ins s6_3Imm:$s6_3, DoubleRegs:$Rtt), - "memd(r29 + #$s6_3) = $Rtt"> { - bits<9> s6_3; - bits<3> Rtt; - - let Inst{12-9} = 0b0101; - let Inst{8-3} = s6_3{8-3}; - let Inst{2-0} = Rtt; - } - -// SS2_storew_sp: Store word. -let Uses = [R29], isCodeGenOnly = 1, mayStore = 1, accessSize = WordAccess in -def SS2_storew_sp: SUBInst < - (outs ), - (ins u5_2Imm:$u5_2, IntRegs:$Rt), - "memw(r29 + #$u5_2) = $Rt"> { - bits<7> u5_2; - bits<4> Rt; - - let Inst{12-9} = 0b0100; - let Inst{8-4} = u5_2{6-2}; - let Inst{3-0} = Rt; - } - -// SL2_jumpr31_fnew: Indirect conditional jump if false. -let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isPredicatedNew = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in -def SL2_jumpr31_fnew: SUBInst < - (outs ), - (ins ), - "if (!p0.new) jumpr:nt r31"> { - let Inst{12-6} = 0b1111111; - let Inst{2-0} = 0b111; - } - -// SA1_clrt: Clear if true. -// SA1_clrt -> SA1_clrtnew -let Uses = [P0], isCodeGenOnly = 1, isPredicated = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -def SA1_clrt: SUBInst < - (outs IntRegs:$Rd), - (ins PredRegs:$Pu), - "if ($Pu) $Rd = #0"> { - bits<4> Rd; - - let Inst{12-9} = 0b1101; - let Inst{6-4} = 0b110; - let Inst{3-0} = Rd; - } - -// SL2_return: Deallocate stack frame and return. -let Defs = [PC, R31, R29, R30], Uses = [R30], isCodeGenOnly = 1, mayLoad = 1, accessSize = DoubleWordAccess, isBranch = 1, isIndirectBranch = 1 in -def SL2_return: SUBInst < - (outs ), - (ins ), - "dealloc_return"> { - let Inst{12-6} = 0b1111101; - let Inst{2} = 0b0; - } - -// SA1_dec: Dec. -let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -def SA1_dec: SUBInst < - (outs IntRegs:$Rd), - (ins IntRegs:$Rs), - "$Rd = add($Rs,#{-1})"> { - bits<4> Rd; - bits<4> Rs; - - let Inst{12-8} = 0b10011; - let Inst{3-0} = Rd; - let Inst{7-4} = Rs; - } - -// SA1_seti: Set immed. -let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0, isExtendable = 1, isExtentSigned = 0, opExtentBits = 6, opExtendable = 1 in -def SA1_seti: SUBInst < - (outs IntRegs:$Rd), - (ins u6_0Ext:$u6), - "$Rd = #$u6"> { - bits<4> Rd; - bits<6> u6; - - let Inst{12-10} = 0b010; - let Inst{3-0} = Rd; - let Inst{9-4} = u6; - } - -// SL2_jumpr31_t: Indirect conditional jump if true. -// SL2_jumpr31_t -> SL2_jumpr31_tnew -let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in -def SL2_jumpr31_t: SUBInst < - (outs ), - (ins ), - "if (p0) jumpr r31"> { - let Inst{12-6} = 0b1111111; - let Inst{2-0} = 0b100; - } - -// SA1_clrfnew: Clear if false. -let Uses = [P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isPredicatedNew = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -def SA1_clrfnew: SUBInst < - (outs IntRegs:$Rd), - (ins PredRegs:$Pu), - "if (!$Pu.new) $Rd = #0"> { - bits<4> Rd; - - let Inst{12-9} = 0b1101; - let Inst{6-4} = 0b101; - let Inst{3-0} = Rd; - } - -// SS1_storew_io: Store word. -let isCodeGenOnly = 1, mayStore = 1, accessSize = WordAccess in -def SS1_storew_io: SUBInst < - (outs ), - (ins IntRegs:$Rs, u4_2Imm:$u4_2, IntRegs:$Rt), - "memw($Rs + #$u4_2) = $Rt"> { - bits<4> Rs; - bits<6> u4_2; - bits<4> Rt; - - let Inst{12} = 0b0; - let Inst{7-4} = Rs; - let Inst{11-8} = u4_2{5-2}; - let Inst{3-0} = Rt; - } - -// SA1_zxtb: Zxtb. -let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -def SA1_zxtb: SUBInst < - (outs IntRegs:$Rd), - (ins IntRegs:$Rs), - "$Rd = and($Rs, #255)"> { - bits<4> Rd; - bits<4> Rs; - - let Inst{12-8} = 0b10111; - let Inst{3-0} = Rd; - let Inst{7-4} = Rs; - } - -// SA1_addsp: Add. -let Uses = [R29], isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -def SA1_addsp: SUBInst < - (outs IntRegs:$Rd), - (ins u6_2Imm:$u6_2), - "$Rd = add(r29, #$u6_2)"> { - bits<4> Rd; - bits<8> u6_2; - - let Inst{12-10} = 0b011; - let Inst{3-0} = Rd; - let Inst{9-4} = u6_2{7-2}; - } - -// SL2_loadri_sp: Load word. -let Uses = [R29], isCodeGenOnly = 1, mayLoad = 1, accessSize = WordAccess, hasNewValue = 1, opNewValue = 0 in -def SL2_loadri_sp: SUBInst < - (outs IntRegs:$Rd), - (ins u5_2Imm:$u5_2), - "$Rd = memw(r29 + #$u5_2)"> { - bits<4> Rd; - bits<7> u5_2; - - let Inst{12-9} = 0b1110; - let Inst{3-0} = Rd; - let Inst{8-4} = u5_2{6-2}; - } - -// SS1_storeb_io: Store byte. -let isCodeGenOnly = 1, mayStore = 1, accessSize = ByteAccess in -def SS1_storeb_io: SUBInst < - (outs ), - (ins IntRegs:$Rs, u4_0Imm:$u4_0, IntRegs:$Rt), - "memb($Rs + #$u4_0) = $Rt"> { - bits<4> Rs; - bits<4> u4_0; - bits<4> Rt; - - let Inst{12} = 0b1; - let Inst{7-4} = Rs; - let Inst{11-8} = u4_0; - let Inst{3-0} = Rt; - } - -// SL2_return_tnew: Deallocate stack frame and return. -let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedNew = 1, mayLoad = 1, accessSize = DoubleWordAccess, isBranch = 1, isIndirectBranch = 1 in -def SL2_return_tnew: SUBInst < - (outs ), - (ins ), - "if (p0.new) dealloc_return:nt"> { - let Inst{12-6} = 0b1111101; - let Inst{2-0} = 0b110; - } - -// SL2_return_fnew: Deallocate stack frame and return. -let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isPredicatedNew = 1, mayLoad = 1, accessSize = DoubleWordAccess, isBranch = 1, isIndirectBranch = 1 in -def SL2_return_fnew: SUBInst < - (outs ), - (ins ), - "if (!p0.new) dealloc_return:nt"> { - let Inst{12-6} = 0b1111101; - let Inst{2-0} = 0b111; - } - -// SA1_zxth: Zxth. -let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -def SA1_zxth: SUBInst < - (outs IntRegs:$Rd), - (ins IntRegs:$Rs), - "$Rd = zxth($Rs)"> { - bits<4> Rd; - bits<4> Rs; - - let Inst{12-8} = 0b10110; - let Inst{3-0} = Rd; - let Inst{7-4} = Rs; - } - diff --git a/lib/Target/Hexagon/HexagonSystemInst.td b/lib/Target/Hexagon/HexagonSystemInst.td deleted file mode 100644 index 629a98749ee..00000000000 --- a/lib/Target/Hexagon/HexagonSystemInst.td +++ /dev/null @@ -1,134 +0,0 @@ -//==- HexagonSystemInst.td - System Instructions for Hexagon -*- tablegen -*-==// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file describes the Hexagon instructions in TableGen format. -// -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// Cache manipulation instructions. -//===----------------------------------------------------------------------===// -let mayStore = 1 in -class ST_MISC_CACHEOP pattern = [], - bits<3> amode, bits<3> type, bits<1> un> - : ST0Inst { - - bits<5> Rs; - bits<5> Rt; - bits<5> Rd; - let Inst{31-28} = 0b1010; - let Inst{27-25} = amode; - let Inst{24-22} = type; - let Inst{21} = un; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - let Inst{4-0} = Rd; -} - -let mayStore = 1 in -class ST_MISC_CACHEOP_SYS pattern = [], - bits<3> amode, bits<3> type, bits<1> un> - : SYSInst { - - bits<5> Rs; - bits<5> Rt; - bits<5> Rd; - let Inst{31-28} = 0b1010; - let Inst{27-25} = amode; - let Inst{24-22} = type; - let Inst{21} = un; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - let Inst{4-0} = Rd; -} - - -let isSolo = 1, Rs = 0, Rt = 0, Rd = 0 in { -def Y2_syncht: ST_MISC_CACHEOP <(outs), (ins), - "syncht" , [], 0b100, 0b001, 0b0>; -} - -let Rt = 0, Rd = 0 in { -let isSoloAin1 = 1 in { - def Y2_dccleana: ST_MISC_CACHEOP <(outs), (ins IntRegs:$Rs), - "dccleana($Rs)", [], 0b000, 0b000, 0b0>; - def Y2_dcinva: ST_MISC_CACHEOP <(outs), (ins IntRegs:$Rs), - "dcinva($Rs)", [], 0b000, 0b000, 0b1>; - def Y2_dccleaninva: ST_MISC_CACHEOP <(outs), (ins IntRegs:$Rs), - "dccleaninva($Rs)", [], 0b000, 0b001, 0b0>; - } -} - -let isSoloAX = 1, hasSideEffects = 1, Rd = 0 in { - def Y4_l2fetch: ST_MISC_CACHEOP_SYS<(outs), (ins IntRegs:$Rs, IntRegs:$Rt), - "l2fetch($Rs, $Rt)", [], 0b011, 0b000, 0b0>; - def Y5_l2fetch: ST_MISC_CACHEOP_SYS<(outs), (ins IntRegs:$Rs, DoubleRegs:$Rt), - "l2fetch($Rs, $Rt)", [], 0b011, 0b010, 0b0>; -} - -let hasSideEffects = 0, isSolo = 1 in -class Y2_INVALIDATE_CACHE - : JRInst < - (outs), (ins IntRegs:$Rs), - #mnemonic#"($Rs)" > { - bits<5> Rs; - - let IClass = 0b0101; - let Inst{27-21} = 0b0110110; - let Inst{20-16} = Rs; - let Inst{13-12} = 0b00; - let Inst{11} = MajOp; - } -// Instruction cache invalidate -def Y2_icinva : Y2_INVALIDATE_CACHE<"icinva", 0b0>; - -// Zero an aligned 32-byte cacheline. -let isSoloAin1 = 1 in -def Y2_dczeroa: ST0Inst <(outs), (ins IntRegs:$Rs), - "dczeroa($Rs)"> { - bits<5> Rs; - let IClass = 0b1010; - let Inst{27-21} = 0b0000110; - let Inst{13} = 0b0; - let Inst{20-16} = Rs; - } - -// Memory synchronization. -let hasSideEffects = 0, isSolo = 1 in -def Y2_isync: JRInst <(outs), (ins), - "isync"> { - let IClass = 0b0101; - let Inst{27-16} = 0b011111000000; - let Inst{13} = 0b0; - let Inst{9-0} = 0b0000000010; - } - -//===----------------------------------------------------------------------===// -// System/User instructions. -//===----------------------------------------------------------------------===// -// traps and pause -let hasSideEffects = 0, isSolo = 1 in -class J2_MISC_TRAP_PAUSE MajOp> - : JRInst - <(outs), (ins u8_0Imm:$u8), - #mnemonic#"(#$u8)"> { - bits<8> u8; - - let IClass = 0b0101; - let Inst{27-24} = 0b0100; - let Inst{23-22} = MajOp; - let Inst{12-8} = u8{7-3}; - let Inst{4-2} = u8{2-0}; - } -def J2_trap0 : J2_MISC_TRAP_PAUSE<"trap0", 0b00>; -def J2_trap1 : J2_MISC_TRAP_PAUSE<"trap1", 0b10>; -def J2_pause : J2_MISC_TRAP_PAUSE<"pause", 0b01>; -