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[AArch64] Allow loads with imp-def to be handled in getMemOpBaseRegImmOfsWidth()

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Summary:
This change will allow loads with imp-def to be clustered in machine-scheduler pass.
areMemAccessesTriviallyDisjoint() can also handle loads with imp-def.

Reviewers: mcrosier, jmolloy, t.p.northover

Subscribers: aemerson, rengolin, mcrosier, llvm-commits

Differential Revision: http://reviews.llvm.org/D18665

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@265051 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jun Bum Lim 2016-03-31 20:53:47 +00:00
parent 9bba5e5a48
commit 2581c8ce4d
3 changed files with 37 additions and 2 deletions
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2
lib/Target/AArch64/AArch64InstrInfo.cpp
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@ -1404,7 +1404,7 @@ bool AArch64InstrInfo::getMemOpBaseRegImmOfsWidth(
const TargetRegisterInfo *TRI) const {
assert(LdSt->mayLoadOrStore() && "Expected a memory operation.");
// Handle only loads/stores with base register followed by immediate offset.
if (LdSt->getNumOperands() != 3)
if (LdSt->getNumExplicitOperands() != 3)
return false;
if (!LdSt->getOperand(1).isReg() || !LdSt->getOperand(2).isImm())
return false;

2
test/CodeGen/AArch64/arm64-abi-varargs.ll
View File

@ -125,7 +125,7 @@ entry:
define void @bar(i32 %x, <4 x i32> %y) nounwind {
entry:
; CHECK-LABEL: bar:
; CHECK: str {{q[0-9]+}}, [sp, #16]
; CHECK: stp {{q[0-9]+}}, {{q[0-9]+}}, [sp, #16]
; CHECK: str {{x[0-9]+}}, [sp]
%x.addr = alloca i32, align 4
%y.addr = alloca <4 x i32>, align 16

35
test/CodeGen/MIR/AArch64/machine-scheduler.mir Normal file
View File

@ -0,0 +1,35 @@
# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass machine-scheduler -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s
--- |
define i64 @load_imp-def(i64* nocapture %P, i32 %v) {
entry:
%0 = bitcast i64* %P to i32*
%1 = load i32, i32* %0
%conv = zext i32 %1 to i64
%arrayidx19 = getelementptr inbounds i64, i64* %P, i64 1
%arrayidx1 = bitcast i64* %arrayidx19 to i32*
store i32 %v, i32* %arrayidx1
%2 = load i64, i64* %arrayidx19
%and = and i64 %2, 4294967295
%add = add nuw nsw i64 %and, %conv
ret i64 %add
}
...
---
# CHECK-LABEL: name: load_imp-def
# CHECK: bb.0.entry:
# CHECK: LDRWui %x0, 0
# CHECK: LDRWui %x0, 1
# CHECK: STRWui %w1, %x0, 2
name: load_imp-def
isSSA: true
body: |
bb.0.entry:
liveins: %w1, %x0
%w8 = LDRWui %x0, 1, implicit-def %x8 :: (load 4 from %ir.0)
STRWui killed %w1, %x0, 2 :: (store 4 into %ir.arrayidx1)
%w9 = LDRWui killed %x0, 0, implicit-def %x9 :: (load 4 from %ir.arrayidx19, align 8)
%x0 = ADDXrr killed %x9, killed %x8
RET_ReallyLR implicit %x0
...