mirror of
https://github.com/RPCS3/llvm.git
synced 2025-02-28 22:58:17 +00:00
Change the isel to not break out of the big giant switch. Instead, the
switch should never be exited, so its bottom is now unreachable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23234 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
7cd09cf942
commit
25dae727f3
@ -661,7 +661,7 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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CurDAG->ReplaceAllUsesWith(Op, New);
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N = New.Val;
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}
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break;
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return SDOperand(N, 0);
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}
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case ISD::CopyFromReg: {
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SDOperand Chain = Select(N->getOperand(0));
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@ -680,7 +680,7 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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CurDAG->ReplaceAllUsesWith(Op, New);
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N = New.Val;
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}
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break;
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return SDOperand(N, 0);
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}
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case ISD::Constant: {
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assert(N->getValueType(0) == MVT::i32);
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@ -706,13 +706,13 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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CurDAG->SelectNodeTo(N, PPC::IMPLICIT_DEF_GPR, MVT::i32);
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else
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CurDAG->SelectNodeTo(N, PPC::IMPLICIT_DEF_FP, N->getValueType(0));
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break;
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return SDOperand(N, 0);
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case ISD::FrameIndex: {
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int FI = cast<FrameIndexSDNode>(N)->getIndex();
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CurDAG->SelectNodeTo(N, PPC::ADDI, MVT::i32,
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CurDAG->getTargetFrameIndex(FI, MVT::i32),
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getI32Imm(0));
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break;
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return SDOperand(N, 0);
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}
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case ISD::ConstantPool: {
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Constant *C = cast<ConstantPoolSDNode>(N)->get();
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@ -722,7 +722,7 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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else
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Tmp = CurDAG->getTargetNode(PPC::LIS, MVT::i32, CPI);
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CurDAG->SelectNodeTo(N, PPC::LA, MVT::i32, Tmp, CPI);
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break;
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return SDOperand(N, 0);
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}
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case ISD::GlobalAddress: {
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GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
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@ -737,7 +737,7 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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CurDAG->SelectNodeTo(N, PPC::LWZ, MVT::i32, GA, Tmp);
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else
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CurDAG->SelectNodeTo(N, PPC::LA, MVT::i32, Tmp, GA);
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break;
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return SDOperand(N, 0);
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}
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case ISD::DYNAMIC_STACKALLOC: {
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// FIXME: We are currently ignoring the requested alignment for handling
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@ -770,8 +770,7 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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// Finally, replace the DYNAMIC_STACKALLOC with the copyfromreg.
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CurDAG->ReplaceAllUsesWith(N, Result.Val);
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N = Result.Val;
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break;
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return SDOperand(Result.Val, Op.ResNo);
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}
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case ISD::SIGN_EXTEND_INREG:
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switch(cast<VTSDNode>(N->getOperand(1))->getVT()) {
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@ -783,21 +782,21 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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CurDAG->SelectNodeTo(N, PPC::EXTSB, MVT::i32, Select(N->getOperand(0)));
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break;
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}
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break;
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return SDOperand(N, 0);
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case ISD::CTLZ:
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assert(N->getValueType(0) == MVT::i32);
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CurDAG->SelectNodeTo(N, PPC::CNTLZW, MVT::i32, Select(N->getOperand(0)));
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break;
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return SDOperand(N, 0);
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case PPCISD::FSEL:
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CurDAG->SelectNodeTo(N, PPC::FSEL, N->getValueType(0),
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Select(N->getOperand(0)),
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Select(N->getOperand(1)),
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Select(N->getOperand(2)));
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break;
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return SDOperand(N, 0);
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case PPCISD::FCTIWZ:
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CurDAG->SelectNodeTo(N, PPC::FCTIWZ, N->getValueType(0),
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Select(N->getOperand(0)));
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break;
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return SDOperand(N, 0);
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case ISD::ADD: {
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MVT::ValueType Ty = N->getValueType(0);
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if (Ty == MVT::i32) {
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@ -809,7 +808,7 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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CurDAG->SelectNodeTo(N, PPC::ADD, MVT::i32, Select(N->getOperand(0)),
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Select(N->getOperand(1)));
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}
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break;
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return SDOperand(N, 0);
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}
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if (!NoExcessFPPrecision) { // Match FMA ops
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@ -820,7 +819,7 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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Select(N->getOperand(0).getOperand(0)),
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Select(N->getOperand(0).getOperand(1)),
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Select(N->getOperand(1)));
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break;
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return SDOperand(N, 0);
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} else if (N->getOperand(1).getOpcode() == ISD::MUL &&
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N->getOperand(1).hasOneUse()) {
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++FusedFP; // Statistic
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@ -828,13 +827,13 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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Select(N->getOperand(1).getOperand(0)),
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Select(N->getOperand(1).getOperand(1)),
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Select(N->getOperand(0)));
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break;
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return SDOperand(N, 0);
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}
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}
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CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FADD : PPC::FADDS, Ty,
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Select(N->getOperand(0)), Select(N->getOperand(1)));
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break;
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return SDOperand(N, 0);
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}
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case ISD::SUB: {
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MVT::ValueType Ty = N->getValueType(0);
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@ -846,7 +845,7 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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else
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CurDAG->SelectNodeTo(N, PPC::SUBFIC, Ty, Select(N->getOperand(1)),
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getI32Imm(Lo16(Imm)));
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break;
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return SDOperand(N, 0);
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}
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if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0), N->getOperand(1),
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PPC::ADDIS, PPC::ADDI, true, true)) {
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@ -856,7 +855,7 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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CurDAG->SelectNodeTo(N, PPC::SUBF, Ty, Select(N->getOperand(1)),
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Select(N->getOperand(0)));
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}
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break;
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return SDOperand(N, 0);
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}
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if (!NoExcessFPPrecision) { // Match FMA ops
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@ -867,7 +866,7 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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Select(N->getOperand(0).getOperand(0)),
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Select(N->getOperand(0).getOperand(1)),
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Select(N->getOperand(1)));
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break;
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return SDOperand(N, 0);
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} else if (N->getOperand(1).getOpcode() == ISD::MUL &&
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N->getOperand(1).Val->hasOneUse()) {
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++FusedFP; // Statistic
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@ -875,20 +874,20 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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Select(N->getOperand(1).getOperand(0)),
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Select(N->getOperand(1).getOperand(1)),
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Select(N->getOperand(0)));
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break;
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return SDOperand(N, 0);
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}
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}
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CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FSUB : PPC::FSUBS, Ty,
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Select(N->getOperand(0)),
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Select(N->getOperand(1)));
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break;
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return SDOperand(N, 0);
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}
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case ISD::MUL: {
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unsigned Imm, Opc;
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if (isIntImmediate(N->getOperand(1), Imm) && isInt16(Imm)) {
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CurDAG->SelectNodeTo(N, PPC::MULLI, MVT::i32,
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Select(N->getOperand(0)), getI32Imm(Lo16(Imm)));
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break;
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return SDOperand(N, 0);
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}
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switch (N->getValueType(0)) {
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default: assert(0 && "Unhandled multiply type!");
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@ -898,7 +897,7 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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}
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CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), Select(N->getOperand(0)),
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Select(N->getOperand(1)));
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break;
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return SDOperand(N, 0);
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}
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case ISD::SDIV: {
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unsigned Imm;
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@ -910,7 +909,7 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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getI32Imm(Log2_32(Imm)));
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CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
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Op.getValue(0), Op.getValue(1));
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break;
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return SDOperand(N, 0);
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} else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
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SDOperand Op =
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CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
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@ -920,13 +919,13 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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CurDAG->getTargetNode(PPC::ADDZE, MVT::i32, Op.getValue(0),
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Op.getValue(1));
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CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT);
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break;
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return SDOperand(N, 0);
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} else if (Imm) {
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SDOperand Result = Select(BuildSDIVSequence(N));
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assert(Result.ResNo == 0);
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CurDAG->ReplaceAllUsesWith(Op, Result);
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N = Result.Val;
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break;
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return SDOperand(N, 0);
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}
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}
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@ -939,7 +938,7 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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}
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CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), Select(N->getOperand(0)),
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Select(N->getOperand(1)));
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break;
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return SDOperand(N, 0);
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}
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case ISD::UDIV: {
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// If this is a divide by constant, we can emit code using some magic
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@ -950,23 +949,23 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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assert(Result.ResNo == 0);
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CurDAG->ReplaceAllUsesWith(Op, Result);
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N = Result.Val;
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break;
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return SDOperand(N, 0);
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}
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CurDAG->SelectNodeTo(N, PPC::DIVWU, MVT::i32, Select(N->getOperand(0)),
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Select(N->getOperand(1)));
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break;
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return SDOperand(N, 0);
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}
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case ISD::MULHS:
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assert(N->getValueType(0) == MVT::i32);
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CurDAG->SelectNodeTo(N, PPC::MULHW, MVT::i32, Select(N->getOperand(0)),
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Select(N->getOperand(1)));
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break;
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return SDOperand(N, 0);
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case ISD::MULHU:
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assert(N->getValueType(0) == MVT::i32);
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CurDAG->SelectNodeTo(N, PPC::MULHWU, MVT::i32, Select(N->getOperand(0)),
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Select(N->getOperand(1)));
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break;
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return SDOperand(N, 0);
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case ISD::AND: {
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unsigned Imm;
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// If this is an and of a value rotated between 0 and 31 bits and then and'd
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@ -984,7 +983,7 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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}
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CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Val, getI32Imm(SH),
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getI32Imm(MB), getI32Imm(ME));
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break;
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return SDOperand(N, 0);
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}
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// Finally, check for the case where we are being asked to select
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// and (not(a), b) or and (a, not(b)) which can be selected as andc.
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@ -997,20 +996,20 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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else
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CurDAG->SelectNodeTo(N, PPC::AND, MVT::i32, Select(N->getOperand(0)),
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Select(N->getOperand(1)));
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break;
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return SDOperand(N, 0);
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}
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case ISD::OR:
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if (SDNode *I = SelectBitfieldInsert(N)) {
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CurDAG->ReplaceAllUsesWith(Op, SDOperand(I, 0));
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N = I;
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break;
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return SDOperand(N, 0);
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}
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if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0),
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N->getOperand(1),
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PPC::ORIS, PPC::ORI)) {
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CurDAG->ReplaceAllUsesWith(Op, SDOperand(I, 0));
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N = I;
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break;
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return SDOperand(N, 0);
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}
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// Finally, check for the case where we are being asked to select
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// 'or (not(a), b)' or 'or (a, not(b))' which can be selected as orc.
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@ -1023,7 +1022,7 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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else
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CurDAG->SelectNodeTo(N, PPC::OR, MVT::i32, Select(N->getOperand(0)),
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Select(N->getOperand(1)));
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break;
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return SDOperand(N, 0);
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case ISD::XOR:
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// Check whether or not this node is a logical 'not'. This is represented
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// by llvm as a xor with the constant value -1 (all bits set). If this is a
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@ -1042,7 +1041,7 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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Val.getOperand(1));
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else
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CurDAG->SelectNodeTo(N, PPC::NOR, MVT::i32, Val, Val);
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break;
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return SDOperand(N, 0);
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}
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// If this is a xor with an immediate other than -1, then codegen it as high
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// and low 16 bit immediate xors.
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@ -1051,7 +1050,7 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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PPC::XORIS, PPC::XORI)) {
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CurDAG->ReplaceAllUsesWith(Op, SDOperand(I, 0));
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N = I;
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break;
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return SDOperand(N, 0);
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}
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// Finally, check for the case where we are being asked to select
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// xor (not(a), b) which is equivalent to not(xor a, b), which is eqv
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@ -1062,7 +1061,7 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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else
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CurDAG->SelectNodeTo(N, PPC::XOR, MVT::i32, Select(N->getOperand(0)),
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Select(N->getOperand(1)));
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break;
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return SDOperand(N, 0);
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case ISD::SHL: {
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unsigned Imm, SH, MB, ME;
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if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
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@ -1076,7 +1075,7 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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else
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CurDAG->SelectNodeTo(N, PPC::SLW, MVT::i32, Select(N->getOperand(0)),
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Select(N->getOperand(1)));
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break;
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return SDOperand(N, 0);
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}
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case ISD::SRL: {
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unsigned Imm, SH, MB, ME;
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@ -1091,7 +1090,7 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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else
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CurDAG->SelectNodeTo(N, PPC::SRW, MVT::i32, Select(N->getOperand(0)),
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Select(N->getOperand(1)));
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break;
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return SDOperand(N, 0);
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}
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case ISD::SRA: {
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unsigned Imm, SH, MB, ME;
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@ -1106,24 +1105,24 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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else
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CurDAG->SelectNodeTo(N, PPC::SRAW, MVT::i32, Select(N->getOperand(0)),
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Select(N->getOperand(1)));
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break;
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return SDOperand(N, 0);
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}
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case ISD::FABS:
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CurDAG->SelectNodeTo(N, PPC::FABS, N->getValueType(0),
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Select(N->getOperand(0)));
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break;
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return SDOperand(N, 0);
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case ISD::FP_EXTEND:
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assert(MVT::f64 == N->getValueType(0) &&
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MVT::f32 == N->getOperand(0).getValueType() && "Illegal FP_EXTEND");
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// We need to emit an FMR to make sure that the result has the right value
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// type.
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CurDAG->SelectNodeTo(N, PPC::FMR, MVT::f64, Select(N->getOperand(0)));
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break;
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return SDOperand(N, 0);
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case ISD::FP_ROUND:
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assert(MVT::f32 == N->getValueType(0) &&
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MVT::f64 == N->getOperand(0).getValueType() && "Illegal FP_ROUND");
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CurDAG->SelectNodeTo(N, PPC::FRSP, MVT::f32, Select(N->getOperand(0)));
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break;
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return SDOperand(N, 0);
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case ISD::FNEG: {
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SDOperand Val = Select(N->getOperand(0));
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MVT::ValueType Ty = N->getValueType(0);
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@ -1146,17 +1145,17 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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else
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CurDAG->SelectNodeTo(N, Opc, Ty, Val.getOperand(0),
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Val.getOperand(1), Val.getOperand(2));
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break;
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return SDOperand(N, 0);
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}
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}
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CurDAG->SelectNodeTo(N, PPC::FNEG, Ty, Val);
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break;
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return SDOperand(N, 0);
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}
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case ISD::FSQRT: {
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MVT::ValueType Ty = N->getValueType(0);
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CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FSQRT : PPC::FSQRTS, Ty,
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Select(N->getOperand(0)));
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break;
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return SDOperand(N, 0);
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}
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||||
|
||||
case ISD::ADD_PARTS: {
|
||||
@ -1242,7 +1241,7 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
|
||||
|
||||
CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
|
||||
Op1, Op2, Select(N->getOperand(0)));
|
||||
break;
|
||||
return SDOperand(N, Op.ResNo);
|
||||
}
|
||||
|
||||
case ISD::TRUNCSTORE:
|
||||
@ -1269,7 +1268,7 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
|
||||
|
||||
CurDAG->SelectNodeTo(N, Opc, MVT::Other, Select(N->getOperand(1)),
|
||||
AddrOp1, AddrOp2, Select(N->getOperand(0)));
|
||||
break;
|
||||
return SDOperand(N, 0);
|
||||
}
|
||||
|
||||
case ISD::SETCC: {
|
||||
@ -1306,7 +1305,7 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
break;
|
||||
return SDOperand(N, 0);
|
||||
} else if (Imm == ~0U) { // setcc op, -1
|
||||
SDOperand Op = Select(N->getOperand(0));
|
||||
switch (CC) {
|
||||
@ -1340,7 +1339,7 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
|
||||
CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, getI32Imm(1));
|
||||
break;
|
||||
}
|
||||
break;
|
||||
return SDOperand(N, 0);
|
||||
}
|
||||
}
|
||||
|
||||
@ -1376,7 +1375,7 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
|
||||
CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
|
||||
}
|
||||
|
||||
break;
|
||||
return SDOperand(N, 0);
|
||||
}
|
||||
|
||||
case ISD::SELECT_CC: {
|
||||
@ -1394,7 +1393,7 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
|
||||
LHS, getI32Imm(~0U));
|
||||
CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, Tmp, LHS,
|
||||
Tmp.getValue(1));
|
||||
break;
|
||||
return SDOperand(N, 0);
|
||||
}
|
||||
|
||||
SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
|
||||
@ -1405,7 +1404,7 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
|
||||
CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), CCReg,
|
||||
Select(N->getOperand(2)), Select(N->getOperand(3)),
|
||||
getI32Imm(BROpc));
|
||||
break;
|
||||
return SDOperand(N, 0);
|
||||
}
|
||||
|
||||
case ISD::CALLSEQ_START:
|
||||
@ -1415,7 +1414,7 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
|
||||
PPC::ADJCALLSTACKDOWN : PPC::ADJCALLSTACKUP;
|
||||
CurDAG->SelectNodeTo(N, Opc, MVT::Other,
|
||||
getI32Imm(Amt), Select(N->getOperand(0)));
|
||||
break;
|
||||
return SDOperand(N, 0);
|
||||
}
|
||||
case ISD::CALL:
|
||||
case ISD::TAILCALL: {
|
||||
@ -1543,12 +1542,12 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
|
||||
|
||||
// Finally, select this to a blr (return) instruction.
|
||||
CurDAG->SelectNodeTo(N, PPC::BLR, MVT::Other, Chain);
|
||||
break;
|
||||
return SDOperand(N, 0);
|
||||
}
|
||||
case ISD::BR:
|
||||
CurDAG->SelectNodeTo(N, PPC::B, MVT::Other, N->getOperand(1),
|
||||
Select(N->getOperand(0)));
|
||||
break;
|
||||
return SDOperand(N, 0);
|
||||
case ISD::BR_CC:
|
||||
case ISD::BRTWOWAY_CC: {
|
||||
SDOperand Chain = Select(N->getOperand(0));
|
||||
@ -1584,9 +1583,12 @@ SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
|
||||
getI32Imm(Opc), N->getOperand(4),
|
||||
CurDAG->getBasicBlock(It), Chain);
|
||||
}
|
||||
break;
|
||||
return SDOperand(N, 0);
|
||||
}
|
||||
}
|
||||
|
||||
assert(0 && "Unreachable!");
|
||||
abort();
|
||||
return SDOperand(N, Op.ResNo);
|
||||
}
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user