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Make tBX_RET and tBX_RET_vararg predicable.

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The normal tBX instruction is predicable, so there's no reason the
pseudos for using it as a return shouldn't be. Gives us some nice code-gen
improvements as can be seen by the test changes. In particular, several
tests now have to disable if-conversion because it works too well and defeats
the test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134746 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-07-08 21:50:04 +00:00
parent f29608267b
commit 25e6d48220
7 changed files with 24 additions and 16 deletions
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5
lib/Target/ARM/ARMConstantIslandPass.cpp
View File

@ -1538,7 +1538,10 @@ bool ARMConstantIslands::UndoLRSpillRestore() {
if (MI->getOpcode() == ARM::tPOP_RET &&
MI->getOperand(2).getReg() == ARM::PC &&
MI->getNumExplicitOperands() == 3) {
BuildMI(MI->getParent(), MI->getDebugLoc(), TII->get(ARM::tBX_RET));
// Create the new insn and copy the predicate from the old.
BuildMI(MI->getParent(), MI->getDebugLoc(), TII->get(ARM::tBX_RET))
.addOperand(MI->getOperand(0))
.addOperand(MI->getOperand(1));
MI->eraseFromParent();
MadeChange = true;
}

8
lib/Target/ARM/ARMInstrThumb.td
View File

@ -385,13 +385,13 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
}
let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
def tBX_RET : tPseudoExpand<(outs), (ins), Size2Bytes, IIC_Br,
[(ARMretflag)], (tBX LR, (ops 14, zero_reg))>;
def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), Size2Bytes, IIC_Br,
[(ARMretflag)], (tBX LR, pred:$p)>;
// Alternative return instruction used by vararg functions.
def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm),
def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p),
Size2Bytes, IIC_Br, [],
(tBX GPR:$Rm, (ops 14, zero_reg))>;
(tBX GPR:$Rm, pred:$p)>;
}
// All calls clobber the non-callee saved registers. SP is marked as a use to

4
lib/Target/ARM/Thumb1FrameLowering.cpp
View File

@ -273,8 +273,8 @@ void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF,
emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, VARegSaveSize);
BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg))
.addReg(ARM::R3, RegState::Kill);
AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg))
.addReg(ARM::R3, RegState::Kill));
// erase the old tBX_RET instruction
MBB.erase(MBBI);
}

9
test/CodeGen/Thumb2/machine-licm.ll
View File

@ -8,26 +8,25 @@
define void @t1(i32* nocapture %vals, i32 %c) nounwind {
entry:
; CHECK: t1:
; CHECK: cbz
; CHECK: bxeq lr
%0 = icmp eq i32 %c, 0 ; <i1> [#uses=1]
br i1 %0, label %return, label %bb.nph
bb.nph: ; preds = %entry
; CHECK: BB#1
; CHECK: movw r[[R2:[0-9]+]], :lower16:L_GV$non_lazy_ptr
; CHECK: movt r[[R2]], :upper16:L_GV$non_lazy_ptr
; CHECK: ldr{{(.w)?}} r[[R2b:[0-9]+]], [r[[R2]]
; CHECK: ldr{{.*}}, [r[[R2b]]
; CHECK: LBB0_2
; CHECK: LBB0_
; CHECK-NOT: LCPI0_0:
; PIC: BB#1
; PIC: movw r[[R2:[0-9]+]], :lower16:(L_GV$non_lazy_ptr-(LPC0_0+4))
; PIC: movt r[[R2]], :upper16:(L_GV$non_lazy_ptr-(LPC0_0+4))
; PIC: add r[[R2]], pc
; PIC: ldr{{(.w)?}} r[[R2b:[0-9]+]], [r[[R2]]
; PIC: ldr{{.*}}, [r[[R2b]]
; PIC: LBB0_2
; PIC: LBB0_
; PIC-NOT: LCPI0_0:
; PIC: .section
%.pre = load i32* @GV, align 4 ; <i32> [#uses=1]

6
test/CodeGen/Thumb2/thumb2-bcc.ll
View File

@ -1,5 +1,7 @@
; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
; RUN: llc < %s -march=thumb -mattr=+thumb2 | not grep it
; RUN: llc < %s -ifcvt-limit=0 -march=thumb -mattr=+thumb2 | FileCheck %s
; RUN: llc < %s -ifcvt-limit=0 -march=thumb -mattr=+thumb2 | not grep it
; If-conversion defeats the purpose of this test, which is to check CBZ
; generation, so turn it off.
define i32 @t1(i32 %a, i32 %b, i32 %c) {
; CHECK: t1:

4
test/CodeGen/Thumb2/thumb2-branch.ll
View File

@ -1,4 +1,6 @@
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+thumb2 | FileCheck %s
; RUN: llc < %s -ifcvt-limit=0 -mtriple=thumbv7-apple-darwin -mattr=+thumb2 | FileCheck %s
; If-conversion defeats the purpose of this test, which is to check conditional
; branch generation, so turn it off.
define i32 @f1(i32 %a, i32 %b, i32* %v) {
entry:

4
test/CodeGen/Thumb2/thumb2-ifcvt1.ll
View File

@ -2,8 +2,10 @@
define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
; CHECK: t1:
; CHECK: it ne
; CHECK: ittt ne
; CHECK: cmpne
; CHECK: addne
; CHECK: bxne lr
switch i32 %c, label %cond_next [
i32 1, label %cond_true
i32 7, label %cond_true