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[ARM]: Extend -mfpu options for half-precision and vfpv3xd
Some of the the permissible ARM -mfpu options, which are supported in GCC, are currently not present in llvm/clang.This patch adds the options: 'neon-fp16', 'vfpv3-fp16', 'vfpv3-d16-fp16', 'vfpv3xd' and 'vfpv3xd-fp16. These are related to half-precision floating-point and single precision. Reviewers: rengolin, ranjeet.singh Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10645 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240930 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Javed Absar
parent
048a1eb977
commit
263dd533ee
@ -36,7 +36,11 @@ namespace ARM {
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FK_VFP,
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FK_VFPV2,
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FK_VFPV3,
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FK_VFPV3_FP16,
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FK_VFPV3_D16,
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FK_VFPV3_D16_FP16,
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FK_VFPV3XD,
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FK_VFPV3XD_FP16,
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FK_VFPV4,
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FK_VFPV4_D16,
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FK_FPV4_SP_D16,
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@ -44,6 +48,7 @@ namespace ARM {
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FK_FPV5_SP_D16,
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FK_FP_ARMV8,
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FK_NEON,
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FK_NEON_FP16,
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FK_NEON_VFPV4,
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FK_NEON_FP_ARMV8,
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FK_CRYPTO_NEON_FP_ARMV8,
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@ -51,6 +56,16 @@ namespace ARM {
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FK_LAST
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};
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// FPU Version
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enum FPUVersion {
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FV_NONE = 0,
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FV_VFPV2,
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FV_VFPV3,
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FV_VFPV3_FP16,
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FV_VFPV4,
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FV_VFPV5
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};
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// An FPU name implies one of three levels of Neon support:
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enum NeonSupportLevel {
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NS_None = 0, ///< No Neon
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@ -25,31 +25,37 @@ namespace {
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// List of canonical FPU names (use getFPUSynonym) and which architectural
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// features they correspond to (use getFPUFeatures).
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// FIXME: TableGen this.
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// The entries must appear in the order listed in ARM::FPUKind for correct indexing
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struct {
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const char * Name;
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ARM::FPUKind ID;
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unsigned FPUVersion; ///< Corresponds directly to the FP arch version number.
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ARM::FPUVersion FPUVersion;
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ARM::NeonSupportLevel NeonSupport;
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ARM::FPURestriction Restriction;
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} FPUNames[] = {
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{ "invalid", ARM::FK_INVALID, 0, ARM::NS_None, ARM::FR_None},
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{ "none", ARM::FK_NONE, 0, ARM::NS_None, ARM::FR_None},
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{ "vfp", ARM::FK_VFP, 2, ARM::NS_None, ARM::FR_None},
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{ "vfpv2", ARM::FK_VFPV2, 2, ARM::NS_None, ARM::FR_None},
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{ "vfpv3", ARM::FK_VFPV3, 3, ARM::NS_None, ARM::FR_None},
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{ "vfpv3-d16", ARM::FK_VFPV3_D16, 3, ARM::NS_None, ARM::FR_D16},
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{ "vfpv4", ARM::FK_VFPV4, 4, ARM::NS_None, ARM::FR_None},
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{ "vfpv4-d16", ARM::FK_VFPV4_D16, 4, ARM::NS_None, ARM::FR_D16},
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{ "fpv4-sp-d16", ARM::FK_FPV4_SP_D16, 4, ARM::NS_None, ARM::FR_SP_D16},
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{ "fpv5-d16", ARM::FK_FPV5_D16, 5, ARM::NS_None, ARM::FR_D16},
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{ "fpv5-sp-d16", ARM::FK_FPV5_SP_D16, 5, ARM::NS_None, ARM::FR_SP_D16},
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{ "fp-armv8", ARM::FK_FP_ARMV8, 5, ARM::NS_None, ARM::FR_None},
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{ "neon", ARM::FK_NEON, 3, ARM::NS_Neon, ARM::FR_None},
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{ "neon-vfpv4", ARM::FK_NEON_VFPV4, 4, ARM::NS_Neon, ARM::FR_None},
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{ "neon-fp-armv8", ARM::FK_NEON_FP_ARMV8, 5, ARM::NS_Neon, ARM::FR_None},
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{ "invalid", ARM::FK_INVALID, ARM::FV_NONE, ARM::NS_None, ARM::FR_None},
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{ "none", ARM::FK_NONE, ARM::FV_NONE, ARM::NS_None, ARM::FR_None},
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{ "vfp", ARM::FK_VFP, ARM::FV_VFPV2, ARM::NS_None, ARM::FR_None},
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{ "vfpv2", ARM::FK_VFPV2, ARM::FV_VFPV2, ARM::NS_None, ARM::FR_None},
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{ "vfpv3", ARM::FK_VFPV3, ARM::FV_VFPV3, ARM::NS_None, ARM::FR_None},
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{ "vfpv3-fp16", ARM::FK_VFPV3_FP16, ARM::FV_VFPV3_FP16, ARM::NS_None, ARM::FR_None},
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{ "vfpv3-d16", ARM::FK_VFPV3_D16, ARM::FV_VFPV3, ARM::NS_None, ARM::FR_D16},
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{ "vfpv3-d16-fp16", ARM::FK_VFPV3_D16_FP16, ARM::FV_VFPV3_FP16, ARM::NS_None, ARM::FR_D16},
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{ "vfpv3xd", ARM::FK_VFPV3XD, ARM::FV_VFPV3, ARM::NS_None, ARM::FR_SP_D16},
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{ "vfpv3xd-fp16", ARM::FK_VFPV3XD_FP16, ARM::FV_VFPV3_FP16, ARM::NS_None, ARM::FR_SP_D16},
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{ "vfpv4", ARM::FK_VFPV4, ARM::FV_VFPV4, ARM::NS_None, ARM::FR_None},
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{ "vfpv4-d16", ARM::FK_VFPV4_D16, ARM::FV_VFPV4, ARM::NS_None, ARM::FR_D16},
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{ "fpv4-sp-d16", ARM::FK_FPV4_SP_D16, ARM::FV_VFPV4, ARM::NS_None, ARM::FR_SP_D16},
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{ "fpv5-d16", ARM::FK_FPV5_D16, ARM::FV_VFPV5, ARM::NS_None, ARM::FR_D16},
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{ "fpv5-sp-d16", ARM::FK_FPV5_SP_D16, ARM::FV_VFPV5, ARM::NS_None, ARM::FR_SP_D16},
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{ "fp-armv8", ARM::FK_FP_ARMV8, ARM::FV_VFPV5, ARM::NS_None, ARM::FR_None},
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{ "neon", ARM::FK_NEON, ARM::FV_VFPV3, ARM::NS_Neon, ARM::FR_None},
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{ "neon-fp16", ARM::FK_NEON_FP16, ARM::FV_VFPV3_FP16, ARM::NS_Neon, ARM::FR_None},
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{ "neon-vfpv4", ARM::FK_NEON_VFPV4, ARM::FV_VFPV4, ARM::NS_Neon, ARM::FR_None},
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{ "neon-fp-armv8", ARM::FK_NEON_FP_ARMV8, ARM::FV_VFPV5, ARM::NS_Neon, ARM::FR_None},
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{ "crypto-neon-fp-armv8",
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ARM::FK_CRYPTO_NEON_FP_ARMV8, 5, ARM::NS_Crypto, ARM::FR_None},
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{ "softvfp", ARM::FK_SOFTVFP, 0, ARM::NS_None, ARM::FR_None},
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ARM::FK_CRYPTO_NEON_FP_ARMV8, ARM::FV_VFPV5, ARM::NS_Crypto, ARM::FR_None},
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{ "softvfp", ARM::FK_SOFTVFP, ARM::FV_NONE, ARM::NS_None, ARM::FR_None},
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};
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// List of canonical arch names (use getArchSynonym).
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@ -279,33 +285,41 @@ bool ARMTargetParser::getFPUFeatures(unsigned FPUKind,
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// higher. We also have to make sure to disable fp16 when vfp4 is disabled,
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// as +vfp4 implies +fp16 but -vfp4 does not imply -fp16.
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switch (FPUNames[FPUKind].FPUVersion) {
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case 5:
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case ARM::FV_VFPV5:
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Features.push_back("+fp-armv8");
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break;
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case 4:
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case ARM::FV_VFPV4:
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Features.push_back("+vfp4");
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Features.push_back("-fp-armv8");
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break;
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case 3:
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case ARM::FV_VFPV3_FP16:
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Features.push_back("+vfp3");
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Features.push_back("+fp16");
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Features.push_back("-vfp4");
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Features.push_back("-fp-armv8");
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break;
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case ARM::FV_VFPV3:
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Features.push_back("+vfp3");
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Features.push_back("-fp16");
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Features.push_back("-vfp4");
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Features.push_back("-fp-armv8");
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break;
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case 2:
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case ARM::FV_VFPV2:
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Features.push_back("+vfp2");
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Features.push_back("-vfp3");
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Features.push_back("-fp16");
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Features.push_back("-vfp4");
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Features.push_back("-fp-armv8");
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break;
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case 0:
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case ARM::FV_NONE:
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Features.push_back("-vfp2");
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Features.push_back("-vfp3");
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Features.push_back("-fp16");
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Features.push_back("-vfp4");
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Features.push_back("-fp-armv8");
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break;
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default:
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return false;
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}
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// crypto includes neon, so we handle this similarly to FPU version.
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@ -630,7 +630,7 @@ void ARMAsmPrinter::emitAttributes() {
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} else if (STI.hasVFP4())
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ATS.emitFPU(ARM::FK_NEON_VFPV4);
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else
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ATS.emitFPU(ARM::FK_NEON);
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ATS.emitFPU(STI.hasFP16() ? ARM::FK_NEON_FP16 : ARM::FK_NEON);
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// Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
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if (STI.hasV8Ops())
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ATS.emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
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@ -648,7 +648,13 @@ void ARMAsmPrinter::emitAttributes() {
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? (STI.isFPOnlySP() ? ARM::FK_FPV4_SP_D16 : ARM::FK_VFPV4_D16)
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: ARM::FK_VFPV4);
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else if (STI.hasVFP3())
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ATS.emitFPU(STI.hasD16() ? ARM::FK_VFPV3_D16 : ARM::FK_VFPV3);
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ATS.emitFPU(STI.hasD16()
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// +d16
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? (STI.isFPOnlySP()
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? (STI.hasFP16() ? ARM::FK_VFPV3XD_FP16 : ARM::FK_VFPV3XD)
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: (STI.hasFP16() ? ARM::FK_VFPV3_D16_FP16 : ARM::FK_VFPV3_D16))
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// -d16
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: (STI.hasFP16() ? ARM::FK_VFPV3_FP16 : ARM::FK_VFPV3));
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else if (STI.hasVFP2())
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ATS.emitFPU(ARM::FK_VFPV2);
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}
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@ -797,12 +797,44 @@ void ARMTargetELFStreamer::emitFPUDefaultAttributes() {
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/* OverwriteExisting= */ false);
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break;
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case ARM::FK_VFPV3_FP16:
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setAttributeItem(ARMBuildAttrs::FP_arch,
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ARMBuildAttrs::AllowFPv3A,
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/* OverwriteExisting= */ false);
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setAttributeItem(ARMBuildAttrs::FP_HP_extension,
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ARMBuildAttrs::AllowHPFP,
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/* OverwriteExisting= */ false);
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break;
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case ARM::FK_VFPV3_D16:
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setAttributeItem(ARMBuildAttrs::FP_arch,
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ARMBuildAttrs::AllowFPv3B,
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/* OverwriteExisting= */ false);
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break;
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case ARM::FK_VFPV3_D16_FP16:
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setAttributeItem(ARMBuildAttrs::FP_arch,
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ARMBuildAttrs::AllowFPv3B,
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/* OverwriteExisting= */ false);
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setAttributeItem(ARMBuildAttrs::FP_HP_extension,
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ARMBuildAttrs::AllowHPFP,
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/* OverwriteExisting= */ false);
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break;
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case ARM::FK_VFPV3XD:
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setAttributeItem(ARMBuildAttrs::FP_arch,
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ARMBuildAttrs::AllowFPv3B,
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/* OverwriteExisting= */ false);
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break;
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case ARM::FK_VFPV3XD_FP16:
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setAttributeItem(ARMBuildAttrs::FP_arch,
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ARMBuildAttrs::AllowFPv3B,
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/* OverwriteExisting= */ false);
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setAttributeItem(ARMBuildAttrs::FP_HP_extension,
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ARMBuildAttrs::AllowHPFP,
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/* OverwriteExisting= */ false);
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break;
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case ARM::FK_VFPV4:
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setAttributeItem(ARMBuildAttrs::FP_arch,
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ARMBuildAttrs::AllowFPv4A,
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@ -842,6 +874,18 @@ void ARMTargetELFStreamer::emitFPUDefaultAttributes() {
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/* OverwriteExisting= */ false);
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break;
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case ARM::FK_NEON_FP16:
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setAttributeItem(ARMBuildAttrs::FP_arch,
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ARMBuildAttrs::AllowFPv3A,
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/* OverwriteExisting= */ false);
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setAttributeItem(ARMBuildAttrs::Advanced_SIMD_arch,
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ARMBuildAttrs::AllowNeon,
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/* OverwriteExisting= */ false);
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setAttributeItem(ARMBuildAttrs::FP_HP_extension,
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ARMBuildAttrs::AllowHPFP,
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/* OverwriteExisting= */ false);
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break;
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case ARM::FK_NEON_VFPV4:
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setAttributeItem(ARMBuildAttrs::FP_arch,
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ARMBuildAttrs::AllowFPv4A,
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@ -51,6 +51,13 @@
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; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a17 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A17-FAST
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; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a17 -mattr=-vfp2 | FileCheck %s --check-prefix=CORTEX-A17-NOFPU
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; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a17 -mattr=-vfp2 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A17-NOFPU-FAST
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; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mattr=-neon,+vfp3,+fp16 | FileCheck %s --check-prefix=GENERIC-FPU-VFPV3-FP16
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; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mattr=-neon,+vfp3,+d16,+fp16 | FileCheck %s --check-prefix=GENERIC-FPU-VFPV3-D16-FP16
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; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mattr=-neon,+vfp3,+fp-only-sp,+d16 | FileCheck %s --check-prefix=GENERIC-FPU-VFPV3XD
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; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mattr=-neon,+vfp3,+fp-only-sp,+d16,+fp16 | FileCheck %s --check-prefix=GENERIC-FPU-VFPV3XD-FP16
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; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mattr=+neon,+fp16 | FileCheck %s --check-prefix=GENERIC-FPU-NEON-FP16
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; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a17 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
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; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0 | FileCheck %s --check-prefix=CORTEX-M0
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; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M0-FAST
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@ -1091,7 +1098,7 @@
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; CORTEX-R7: .eabi_attribute 7, 82
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; CORTEX-R7: .eabi_attribute 8, 1
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; CORTEX-R7: .eabi_attribute 9, 2
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; CORTEX-R7: .fpu vfpv3-d16
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; CORTEX-R7: .fpu vfpv3xd
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; CORTEX-R7-NOT: .eabi_attribute 19
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;; We default to IEEE 754 compliance
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; CORTEX-R7: .eabi_attribute 20, 1
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@ -1205,6 +1212,12 @@
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; CORTEX-A72-FAST-NOT: .eabi_attribute 22
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; CORTEX-A72-FAST: .eabi_attribute 23, 1
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; GENERIC-FPU-VFPV3-FP16: .fpu vfpv3-fp16
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; GENERIC-FPU-VFPV3-D16-FP16: .fpu vfpv3-d16-fp16
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; GENERIC-FPU-VFPV3XD: .fpu vfpv3xd
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; GENERIC-FPU-VFPV3XD-FP16: .fpu vfpv3xd-fp16
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; GENERIC-FPU-NEON-FP16: .fpu neon-fp16
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; GENERIC-ARMV8_1-A: .eabi_attribute 6, 14
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; GENERIC-ARMV8_1-A: .eabi_attribute 7, 65
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; GENERIC-ARMV8_1-A: .eabi_attribute 8, 1
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@ -10,7 +10,11 @@
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.fpu vfp
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.fpu vfpv2
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.fpu vfpv3
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.fpu vfpv3-fp16
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.fpu vfpv3-d16
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.fpu vfpv3-d16-fp16
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.fpu vfpv3xd
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.fpu vfpv3xd-fp16
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.fpu vfpv4
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.fpu vfpv4-d16
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.fpu fpv4-sp-d16
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@ -18,6 +22,7 @@
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.fpu fpv5-sp-d16
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.fpu fp-armv8
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.fpu neon
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.fpu neon-fp16
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.fpu neon-vfpv4
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.fpu neon-fp-armv8
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.fpu crypto-neon-fp-armv8
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