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Remove unused NEONFrm and ThumbMiscFrm ARM instruction formats.

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Renumber MiscFrm to 25.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106916 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2010-06-25 23:45:37 +00:00
parent 161476ec34
commit 2653263165
3 changed files with 7 additions and 22 deletions
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4
lib/Target/ARM/ARMBaseInstrInfo.h
View File

@ -116,8 +116,10 @@ namespace ARMII {
// Thumb format // Thumb format
ThumbFrm = 24 << FormShift, ThumbFrm = 24 << FormShift,
// Miscelleaneous format
MiscFrm = 25 << FormShift,
// NEON formats // NEON formats
NEONFrm = 25 << FormShift,
NEONGetLnFrm = 26 << FormShift, NEONGetLnFrm = 26 << FormShift,
NEONSetLnFrm = 27 << FormShift, NEONSetLnFrm = 27 << FormShift,
NEONDupFrm = 28 << FormShift, NEONDupFrm = 28 << FormShift,

6
lib/Target/ARM/ARMInstrFormats.td
View File

@ -50,15 +50,11 @@ def VFPLdStMulFrm : Format<22>;
def VFPMiscFrm : Format<23>; def VFPMiscFrm : Format<23>;
def ThumbFrm : Format<24>; def ThumbFrm : Format<24>;
def MiscFrm : Format<25>;
def NEONFrm : Format<25>;
def NEONGetLnFrm : Format<26>; def NEONGetLnFrm : Format<26>;
def NEONSetLnFrm : Format<27>; def NEONSetLnFrm : Format<27>;
def NEONDupFrm : Format<28>; def NEONDupFrm : Format<28>;
def MiscFrm : Format<29>;
def ThumbMiscFrm : Format<30>;
def NLdStFrm : Format<31>; def NLdStFrm : Format<31>;
def N1RegModImmFrm : Format<32>; def N1RegModImmFrm : Format<32>;
def N2RegFrm : Format<33>; def N2RegFrm : Format<33>;

19
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
View File

@ -2839,12 +2839,6 @@ static bool DisassembleNVTBLFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
return true; return true;
} }
static bool DisassembleNEONFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
unsigned short NumOps, unsigned &NumOpsAdded, BO) {
assert(0 && "Unreachable code!");
return false;
}
// Vector Get Lane (move scalar to ARM core register) Instructions. // Vector Get Lane (move scalar to ARM core register) Instructions.
// VGETLNi32, VGETLNs16, VGETLNs8, VGETLNu16, VGETLNu8: Rt Dn index // VGETLNi32, VGETLNs16, VGETLNs8, VGETLNu16, VGETLNu8: Rt Dn index
static bool DisassembleNEONGetLnFrm(MCInst &MI, unsigned Opcode, uint32_t insn, static bool DisassembleNEONGetLnFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
@ -3060,13 +3054,6 @@ static bool DisassembleMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
return false; return false;
} }
static bool DisassembleThumbMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
unsigned short NumOps, unsigned &NumOpsAdded, BO) {
assert(0 && "Unexpected thumb misc. instruction!");
return false;
}
/// FuncPtrs - FuncPtrs maps ARMFormat to its corresponding DisassembleFP. /// FuncPtrs - FuncPtrs maps ARMFormat to its corresponding DisassembleFP.
/// We divide the disassembly task into different categories, with each one /// We divide the disassembly task into different categories, with each one
/// corresponding to a specific instruction encoding format. There could be /// corresponding to a specific instruction encoding format. There could be
@ -3098,12 +3085,12 @@ static const DisassembleFP FuncPtrs[] = {
&DisassembleVFPLdStMulFrm, &DisassembleVFPLdStMulFrm,
&DisassembleVFPMiscFrm, &DisassembleVFPMiscFrm,
&DisassembleThumbFrm, &DisassembleThumbFrm,
&DisassembleNEONFrm, &DisassembleMiscFrm,
&DisassembleNEONGetLnFrm, &DisassembleNEONGetLnFrm,
&DisassembleNEONSetLnFrm, &DisassembleNEONSetLnFrm,
&DisassembleNEONDupFrm, &DisassembleNEONDupFrm,
&DisassembleMiscFrm, 0,
&DisassembleThumbMiscFrm, 0,
// VLD and VST (including one lane) Instructions. // VLD and VST (including one lane) Instructions.
&DisassembleNLdSt, &DisassembleNLdSt,