RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2025-01-26 12:46:00 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Add or reg-reg pattern.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75914 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov 2009-07-16 13:30:53 +00:00
parent 0676d2887a
commit 26ba0b1ec5
3 changed files with 23 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
lib/Target/SystemZ/SystemZInstrInfo.td
View File

@ -69,5 +69,13 @@ def ADD64ri : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
[(set GR64:$dst, (add GR64:$src1, imm:$src2)),
(implicit PSW)]>;
let isCommutable = 1 in { // X = OR Y, Z == X = OR Z, Y
// FIXME: Provide proper encoding!
def OR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
"ogr\t{$dst, $src2}",
[(set GR64:$dst, (or GR64:$src1, GR64:$src2))]>;
}
// FIXME: provide patterns for masked or-with-imm
} // Defs = [PSW]
} // isTwoAddress = 1

6
test/CodeGen/SystemZ/02-RetOr.ll Normal file
View File

@ -0,0 +1,6 @@
; RUN: llvm-as < %s | llc
define i64 @foo(i64 %a, i64 %b) {
entry:
%c = or i64 %a, %b
ret i64 %c
}

9
test/CodeGen/SystemZ/02-RetOrImm.ll Normal file
View File

@ -0,0 +1,9 @@
; RUN: llvm-as < %s | llc
define i64 @foo(i64 %a, i64 %b) {
entry:
%c = or i64 %a, 1
ret i64 %c
}
; FIXME: SystemZ has 4 or reg-imm instructions depending on imm,
; we need to support them someday.