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[IfConversion] Bugfix: Don't use undef flag while adding use operands.

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IfConversion used to always add the undef flag when adding a use operand
on a newly predicated instruction. This would be an operand for the register
being conditionally redefined. Due to the undef flag, the liveness of this
register prior to the predicated instruction would get lost.

This patch changes this so that such use operands are added only when the
register is live, without the undef flag.

This was reverted but pushed again now, for details follow link below.

Reviewed by Quentin Colombet.
http://reviews.llvm.org/D209077

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277571 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jonas Paulsson 2016-08-03 05:46:35 +00:00
parent 8843600753
commit 26d2b7b824
1 changed files with 16 additions and 3 deletions
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19
lib/CodeGen/IfConversion.cpp
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@ -1070,8 +1070,19 @@ void IfConverter::RemoveExtraEdges(BBInfo &BBI) {
}
/// Behaves like LiveRegUnits::StepForward() but also adds implicit uses to all
/// values defined in MI which are not live/used by MI.
/// values defined in MI which are also live/used by MI.
static void UpdatePredRedefs(MachineInstr &MI, LivePhysRegs &Redefs) {
const TargetRegisterInfo *TRI = MI.getParent()->getParent()
->getSubtarget().getRegisterInfo();
// Before stepping forward past MI, remember which regs were live
// before MI. This is needed to set the Undef flag only when reg is
// dead.
SparseSet<unsigned> LiveBeforeMI;
LiveBeforeMI.setUniverse(TRI->getNumRegs());
for (auto &Reg : Redefs)
LiveBeforeMI.insert(Reg);
SmallVector<std::pair<unsigned, const MachineOperand*>, 4> Clobbers;
Redefs.stepForward(MI, Clobbers);
@ -1085,7 +1096,8 @@ static void UpdatePredRedefs(MachineInstr &MI, LivePhysRegs &Redefs) {
if (Op.isRegMask()) {
// First handle regmasks. They clobber any entries in the mask which
// means that we need a def for those registers.
MIB.addReg(Reg.first, RegState::Implicit | RegState::Undef);
if (LiveBeforeMI.count(Reg.first))
MIB.addReg(Reg.first, RegState::Implicit);
// We also need to add an implicit def of this register for the later
// use to read from.
@ -1102,7 +1114,8 @@ static void UpdatePredRedefs(MachineInstr &MI, LivePhysRegs &Redefs) {
if (Redefs.contains(Op.getReg()))
Op.setIsDead(false);
}
MIB.addReg(Reg.first, RegState::Implicit | RegState::Undef);
if (LiveBeforeMI.count(Reg.first))
MIB.addReg(Reg.first, RegState::Implicit);
}
}