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TableGen: Add hasNoSchedulingInfo to instructions

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This introduces a new flag that indicates that a specific instruction
will never be present when the MachineScheduler runs and therefore needs
no scheduling information.

This is in preparation for an upcoming commit which checks completeness
of a scheduling model when tablegen runs.

Differential Revision: http://reviews.llvm.org/D17728

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262383 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matthias Braun 2016-03-01 20:03:11 +00:00
parent 47e3ade685
commit 279476d30d
4 changed files with 12 additions and 2 deletions
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9
include/llvm/Target/Target.td
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@ -427,6 +427,11 @@ class Instruction {
// Is this instruction a pseudo instruction for use by the assembler parser.
bit isAsmParserOnly = 0;
// This instruction is not expected to be queried for scheduling latencies
// and therefore needs no scheduling information even for a complete
// scheduling model.
bit hasNoSchedulingInfo = 0;
InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
// Scheduling information from TargetSchedule.td.
@ -765,7 +770,8 @@ class InstrInfo {
// Standard Pseudo Instructions.
// This list must match TargetOpcodes.h and CodeGenTarget.cpp.
// Only these instructions are allowed in the TargetOpcode namespace.
let isCodeGenOnly = 1, isPseudo = 1, Namespace = "TargetOpcode" in {
let isCodeGenOnly = 1, isPseudo = 1, hasNoSchedulingInfo = 1,
Namespace = "TargetOpcode" in {
def PHI : Instruction {
let OutOperandList = (outs);
let InOperandList = (ins variable_ops);
@ -857,6 +863,7 @@ def COPY : Instruction {
let AsmString = "";
let hasSideEffects = 0;
let isAsCheapAsAMove = 1;
let hasNoSchedulingInfo = 0;
}
def BUNDLE : Instruction {
let OutOperandList = (outs);

1
utils/TableGen/CodeGenInstruction.cpp
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@ -324,6 +324,7 @@ CodeGenInstruction::CodeGenInstruction(Record *R)
isExtractSubreg = R->getValueAsBit("isExtractSubreg");
isInsertSubreg = R->getValueAsBit("isInsertSubreg");
isConvergent = R->getValueAsBit("isConvergent");
hasNoSchedulingInfo = R->getValueAsBit("hasNoSchedulingInfo");
bool Unset;
mayLoad = R->getValueAsBitOrUnset("mayLoad", Unset);

1
utils/TableGen/CodeGenInstruction.h
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@ -257,6 +257,7 @@ namespace llvm {
bool isExtractSubreg : 1;
bool isInsertSubreg : 1;
bool isConvergent : 1;
bool hasNoSchedulingInfo : 1;
std::string DeprecatedReason;
bool HasComplexDeprecationPredicate;

3
utils/TableGen/CodeGenSchedule.cpp
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@ -527,7 +527,8 @@ void CodeGenSchedModels::collectSchedClasses() {
std::string InstName = Inst->TheDef->getName();
unsigned SCIdx = InstrClassMap.lookup(Inst->TheDef);
if (!SCIdx) {
dbgs() << "No machine model for " << Inst->TheDef->getName() << '\n';
if (!Inst->hasNoSchedulingInfo)
dbgs() << "No machine model for " << Inst->TheDef->getName() << '\n';
continue;
}
CodeGenSchedClass &SC = getSchedClass(SCIdx);