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[Hexagon] Creating HexagonMCInstrInfo namespace as landing zone for static functions detached from HexagonMCInst.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229885 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
0f842f925d
commit
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@ -5,6 +5,7 @@ add_llvm_library(LLVMHexagonDesc
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HexagonMCAsmInfo.cpp
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HexagonMCAsmInfo.cpp
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HexagonMCCodeEmitter.cpp
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HexagonMCCodeEmitter.cpp
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HexagonMCInst.cpp
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HexagonMCInst.cpp
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HexagonMCInstrInfo.cpp
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HexagonMCTargetDesc.cpp
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HexagonMCTargetDesc.cpp
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)
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)
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@ -11,6 +11,7 @@
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#include "MCTargetDesc/HexagonBaseInfo.h"
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#include "MCTargetDesc/HexagonBaseInfo.h"
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#include "MCTargetDesc/HexagonMCCodeEmitter.h"
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#include "MCTargetDesc/HexagonMCCodeEmitter.h"
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#include "MCTargetDesc/HexagonMCInst.h"
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#include "MCTargetDesc/HexagonMCInst.h"
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#include "MCTargetDesc/HexagonMCInstrInfo.h"
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#include "MCTargetDesc/HexagonMCTargetDesc.h"
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#include "MCTargetDesc/HexagonMCTargetDesc.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCCodeEmitter.h"
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@ -51,14 +52,15 @@ void emitLittleEndian(uint64_t Binary, raw_ostream &OS) {
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HexagonMCCodeEmitter::HexagonMCCodeEmitter(MCInstrInfo const &aMII,
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HexagonMCCodeEmitter::HexagonMCCodeEmitter(MCInstrInfo const &aMII,
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MCSubtargetInfo const &aMST,
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MCSubtargetInfo const &aMST,
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MCContext &aMCT)
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MCContext &aMCT)
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: MST(aMST), MCT(aMCT) {}
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: MST(aMST), MCT(aMCT), MCII (aMII) {}
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void HexagonMCCodeEmitter::EncodeInstruction(MCInst const &MI, raw_ostream &OS,
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void HexagonMCCodeEmitter::EncodeInstruction(MCInst const &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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SmallVectorImpl<MCFixup> &Fixups,
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MCSubtargetInfo const &STI) const {
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MCSubtargetInfo const &STI) const {
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HexagonMCInst const &HMB = static_cast<HexagonMCInst const &>(MI);
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HexagonMCInst const &HMB = static_cast<HexagonMCInst const &>(MI);
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uint64_t Binary = getBinaryCodeForInstr(HMB, Fixups, STI) | getPacketBits(HMB);
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uint64_t Binary = getBinaryCodeForInstr(HMB, Fixups, STI) | getPacketBits(HMB);
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assert(HMB.getDesc().getSize() == 4 && "All instructions should be 32bit");
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assert(HexagonMCInstrInfo::getDesc(MCII, HMB).getSize() == 4 &&
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"All instructions should be 32bit");
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emitLittleEndian(Binary, OS);
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emitLittleEndian(Binary, OS);
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++MCNumEmitted;
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++MCNumEmitted;
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}
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}
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@ -28,6 +28,7 @@ namespace llvm {
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class HexagonMCCodeEmitter : public MCCodeEmitter {
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class HexagonMCCodeEmitter : public MCCodeEmitter {
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MCSubtargetInfo const &MST;
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MCSubtargetInfo const &MST;
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MCContext &MCT;
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MCContext &MCT;
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MCInstrInfo const &MCII;
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public:
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public:
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HexagonMCCodeEmitter(MCInstrInfo const &aMII, MCSubtargetInfo const &aMST,
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HexagonMCCodeEmitter(MCInstrInfo const &aMII, MCSubtargetInfo const &aMST,
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@ -13,6 +13,7 @@
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#include "MCTargetDesc/HexagonBaseInfo.h"
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#include "MCTargetDesc/HexagonBaseInfo.h"
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#include "MCTargetDesc/HexagonMCInst.h"
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#include "MCTargetDesc/HexagonMCInst.h"
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#include "MCTargetDesc/HexagonMCInstrInfo.h"
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#include "MCTargetDesc/HexagonMCTargetDesc.h"
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#include "MCTargetDesc/HexagonMCTargetDesc.h"
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using namespace llvm;
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using namespace llvm;
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@ -64,21 +65,17 @@ void HexagonMCInst::resetPacket() {
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setPacketEnd(false);
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setPacketEnd(false);
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}
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}
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MCInstrDesc const &HexagonMCInst::getDesc() const {
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return (MCII->get(getOpcode()));
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}
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// Return the Hexagon ISA class for the insn.
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// Return the Hexagon ISA class for the insn.
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unsigned HexagonMCInst::getType() const {
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unsigned HexagonMCInst::getType() const {
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const uint64_t F = getDesc().TSFlags;
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const uint64_t F = HexagonMCInstrInfo::getDesc(*MCII, *this).TSFlags;
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return ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
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return ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
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}
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}
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// Return whether the insn is an actual insn.
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// Return whether the insn is an actual insn.
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bool HexagonMCInst::isCanon() const {
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bool HexagonMCInst::isCanon() const {
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return (!getDesc().isPseudo() && !isPrefix() &&
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return (!HexagonMCInstrInfo::getDesc(*MCII, *this).isPseudo() &&
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getType() != HexagonII::TypeENDLOOP);
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!isPrefix() && getType() != HexagonII::TypeENDLOOP);
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}
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}
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// Return whether the insn is a prefix.
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// Return whether the insn is a prefix.
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@ -88,25 +85,25 @@ bool HexagonMCInst::isPrefix() const {
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// Return whether the insn is solo, i.e., cannot be in a packet.
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// Return whether the insn is solo, i.e., cannot be in a packet.
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bool HexagonMCInst::isSolo() const {
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bool HexagonMCInst::isSolo() const {
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const uint64_t F = getDesc().TSFlags;
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const uint64_t F = HexagonMCInstrInfo::getDesc(*MCII, *this).TSFlags;
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return ((F >> HexagonII::SoloPos) & HexagonII::SoloMask);
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return ((F >> HexagonII::SoloPos) & HexagonII::SoloMask);
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}
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}
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// Return whether the insn is a new-value consumer.
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// Return whether the insn is a new-value consumer.
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bool HexagonMCInst::isNewValue() const {
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bool HexagonMCInst::isNewValue() const {
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const uint64_t F = getDesc().TSFlags;
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const uint64_t F = HexagonMCInstrInfo::getDesc(*MCII, *this).TSFlags;
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return ((F >> HexagonII::NewValuePos) & HexagonII::NewValueMask);
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return ((F >> HexagonII::NewValuePos) & HexagonII::NewValueMask);
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}
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}
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// Return whether the instruction is a legal new-value producer.
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// Return whether the instruction is a legal new-value producer.
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bool HexagonMCInst::hasNewValue() const {
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bool HexagonMCInst::hasNewValue() const {
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const uint64_t F = getDesc().TSFlags;
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const uint64_t F = HexagonMCInstrInfo::getDesc(*MCII, *this).TSFlags;
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return ((F >> HexagonII::hasNewValuePos) & HexagonII::hasNewValueMask);
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return ((F >> HexagonII::hasNewValuePos) & HexagonII::hasNewValueMask);
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}
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}
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// Return the operand that consumes or produces a new value.
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// Return the operand that consumes or produces a new value.
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const MCOperand &HexagonMCInst::getNewValue() const {
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const MCOperand &HexagonMCInst::getNewValue() const {
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const uint64_t F = getDesc().TSFlags;
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const uint64_t F = HexagonMCInstrInfo::getDesc(*MCII, *this).TSFlags;
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const unsigned O =
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const unsigned O =
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(F >> HexagonII::NewValueOpPos) & HexagonII::NewValueOpMask;
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(F >> HexagonII::NewValueOpPos) & HexagonII::NewValueOpMask;
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const MCOperand &MCO = getOperand(O);
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const MCOperand &MCO = getOperand(O);
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@ -132,7 +129,7 @@ bool HexagonMCInst::isConstExtended(void) const {
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short ExtOpNum = getCExtOpNum();
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short ExtOpNum = getCExtOpNum();
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int MinValue = getMinValue();
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int MinValue = getMinValue();
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int MaxValue = getMaxValue();
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int MaxValue = HexagonMCInstrInfo::getMaxValue(*MCII, *this);
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const MCOperand &MO = getOperand(ExtOpNum);
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const MCOperand &MO = getOperand(ExtOpNum);
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// We could be using an instruction with an extendable immediate and shoehorn
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// We could be using an instruction with an extendable immediate and shoehorn
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@ -154,31 +151,31 @@ bool HexagonMCInst::isConstExtended(void) const {
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// Return whether the instruction must be always extended.
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// Return whether the instruction must be always extended.
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bool HexagonMCInst::isExtended(void) const {
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bool HexagonMCInst::isExtended(void) const {
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const uint64_t F = getDesc().TSFlags;
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const uint64_t F = HexagonMCInstrInfo::getDesc(*MCII, *this).TSFlags;
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return (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
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return (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
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}
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}
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// Return true if the instruction may be extended based on the operand value.
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// Return true if the instruction may be extended based on the operand value.
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bool HexagonMCInst::isExtendable(void) const {
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bool HexagonMCInst::isExtendable(void) const {
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const uint64_t F = getDesc().TSFlags;
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const uint64_t F = HexagonMCInstrInfo::getDesc(*MCII, *this).TSFlags;
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return (F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask;
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return (F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask;
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}
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}
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// Return number of bits in the constant extended operand.
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// Return number of bits in the constant extended operand.
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unsigned HexagonMCInst::getBitCount(void) const {
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unsigned HexagonMCInst::getBitCount(void) const {
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const uint64_t F = getDesc().TSFlags;
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const uint64_t F = HexagonMCInstrInfo::getDesc(*MCII, *this).TSFlags;
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return ((F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask);
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return ((F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask);
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}
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}
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// Return constant extended operand number.
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// Return constant extended operand number.
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unsigned short HexagonMCInst::getCExtOpNum(void) const {
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unsigned short HexagonMCInst::getCExtOpNum(void) const {
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const uint64_t F = getDesc().TSFlags;
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const uint64_t F = HexagonMCInstrInfo::getDesc(*MCII, *this).TSFlags;
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return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask);
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return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask);
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}
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}
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// Return whether the operand can be constant extended.
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// Return whether the operand can be constant extended.
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bool HexagonMCInst::isOperandExtended(const unsigned short OperandNum) const {
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bool HexagonMCInst::isOperandExtended(const unsigned short OperandNum) const {
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const uint64_t F = getDesc().TSFlags;
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const uint64_t F = HexagonMCInstrInfo::getDesc(*MCII, *this).TSFlags;
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return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask) ==
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return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask) ==
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OperandNum;
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OperandNum;
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}
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}
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@ -186,7 +183,7 @@ bool HexagonMCInst::isOperandExtended(const unsigned short OperandNum) const {
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// Return the min value that a constant extendable operand can have
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// Return the min value that a constant extendable operand can have
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// without being extended.
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// without being extended.
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int HexagonMCInst::getMinValue(void) const {
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int HexagonMCInst::getMinValue(void) const {
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const uint64_t F = getDesc().TSFlags;
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const uint64_t F = HexagonMCInstrInfo::getDesc(*MCII, *this).TSFlags;
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unsigned isSigned =
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unsigned isSigned =
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(F >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask;
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(F >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask;
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unsigned bits = (F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask;
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unsigned bits = (F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask;
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@ -196,17 +193,3 @@ int HexagonMCInst::getMinValue(void) const {
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else
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else
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return 0;
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return 0;
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}
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}
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// Return the max value that a constant extendable operand can have
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// without being extended.
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int HexagonMCInst::getMaxValue(void) const {
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const uint64_t F = getDesc().TSFlags;
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unsigned isSigned =
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(F >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask;
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unsigned bits = (F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask;
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if (isSigned) // if value is signed
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return ~(-1U << (bits - 1));
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else
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return ~(-1U << bits);
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}
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@ -52,8 +52,6 @@ public:
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// Return the Hexagon ISA class for the insn.
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// Return the Hexagon ISA class for the insn.
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unsigned getType() const;
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unsigned getType() const;
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MCInstrDesc const &getDesc() const;
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// Return whether the insn is an actual insn.
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// Return whether the insn is an actual insn.
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bool isCanon() const;
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bool isCanon() const;
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@ -94,10 +92,6 @@ private:
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// Return the min value that a constant extendable operand can have
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// Return the min value that a constant extendable operand can have
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// without being extended.
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// without being extended.
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int getMinValue() const;
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int getMinValue() const;
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// Return the max value that a constant extendable operand can have
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// without being extended.
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int getMaxValue() const;
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};
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};
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}
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}
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37
lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
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37
lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
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@ -0,0 +1,37 @@
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//===- HexagonMCInstrInfo.cpp - Hexagon sub-class of MCInst ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This class extends MCInstrInfo to allow Hexagon specific MCInstr queries
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//
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//===----------------------------------------------------------------------===//
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#include "HexagonMCInstrInfo.h"
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#include "HexagonBaseInfo.h"
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#include "llvm/MC/MCInstrInfo.h"
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namespace llvm {
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MCInstrDesc const &HexagonMCInstrInfo::getDesc(MCInstrInfo const &MCII,
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MCInst const &MCI) {
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return (MCII.get(MCI.getOpcode()));
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}
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// Return the max value that a constant extendable operand can have
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// without being extended.
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int HexagonMCInstrInfo::getMaxValue(MCInstrInfo const &MCII,
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MCInst const &MCI) {
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const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
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unsigned isSigned =
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(F >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask;
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unsigned bits = (F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask;
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if (isSigned) // if value is signed
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return ~(-1U << (bits - 1));
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else
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return ~(-1U << bits);
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}
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}
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29
lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h
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29
lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h
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@ -0,0 +1,29 @@
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//===- HexagonMCInstrInfo.cpp - Hexagon sub-class of MCInst ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Utility functions for Hexagon specific MCInst queries
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCINSTRINFO_H
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#define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCINSTRINFO_H
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namespace llvm {
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class MCInstrDesc;
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class MCInstrInfo;
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class MCInst;
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namespace HexagonMCInstrInfo {
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MCInstrDesc const &getDesc(MCInstrInfo const &MCII, MCInst const &MCI);
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// Return the max value that a constant extendable operand can have
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// without being extended.
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int getMaxValue(MCInstrInfo const &MCII, MCInst const &MCI);
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}
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}
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#endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCINSTRINFO_H
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