RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2025-01-18 16:03:17 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Fix for PR3225: disable a broken optimization in

Browse Source 
DAGTypeLegalizer::ExpandShiftWithKnownAmountBit.

In terms of restoring the optimization, the best fix here isn't 
obvious... any ideas?



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61119 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eli Friedman 2008-12-17 03:35:17 +00:00
parent 2d0484c02c
commit 28dc98f752
2 changed files with 22 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
View File

@ -1211,6 +1211,8 @@ ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
}
}
#if 0
// FIXME: This code is broken for shifts with a zero amount!
// If we know that all of the high bits of the shift amount are zero, then we
// can do this as a couple of simple shifts.
if ((KnownZero & HighBitMask) == HighBitMask) {
@ -1232,6 +1234,7 @@ ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
DAG.getNode(Op2, NVT, InL, Amt2));
return true;
}
#endif
return false;
}

19
test/CodeGen/X86/2008-12-16-BadShift.ll Normal file
View File

@ -0,0 +1,19 @@
; RUN: llvm-as < %s | llc | not grep shrl
; Note: this test is really trying to make sure that the shift
; returns the right result; shrl is most likely wrong,
; but if CodeGen starts legitimately using an shrl here,
; please adjust the test appropriately.
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
target triple = "i386-pc-linux-gnu"
@.str = internal constant [6 x i8] c"%lld\0A\00" ; <[6 x i8]*> [#uses=1]
define i64 @mebbe_shift(i32 %xx, i32 %test) nounwind {
entry:
%conv = zext i32 %xx to i64 ; <i64> [#uses=1]
%tobool = icmp ne i32 %test, 0 ; <i1> [#uses=1]
%shl = select i1 %tobool, i64 3, i64 0 ; <i64> [#uses=1]
%x.0 = shl i64 %conv, %shl ; <i64> [#uses=1]
ret i64 %x.0
}