RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2024-11-25 04:39:51 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack

Browse Source 
instructions to subtarget features and update tests to reflect.
PR5717.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103136 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2010-05-05 23:44:43 +00:00
parent 1cc0d62855
commit 29402132f3
14 changed files with 47 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
lib/Target/ARM/ARM.td
View File

@ -44,6 +44,10 @@ def FeatureThumb2 : SubtargetFeature<"thumb2", "ThumbMode", "Thumb2",
"Enable Thumb2 instructions">; "Enable Thumb2 instructions">;
def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true", def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true",
"Enable half-precision floating point">; "Enable half-precision floating point">;
def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
"Enable divide instructions">;
def FeatureT2ExtractPack: SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
"Enable Thumb2 extract and pack instructions">;
// Some processors have multiply-accumulate instructions that don't // Some processors have multiply-accumulate instructions that don't
// play nicely with other VFP instructions, and it's generally better // play nicely with other VFP instructions, and it's generally better
@ -125,10 +129,11 @@ def : Processor<"arm1156t2f-s", ARMV6Itineraries,
// V7 Processors. // V7 Processors.
def : Processor<"cortex-a8", CortexA8Itineraries, def : Processor<"cortex-a8", CortexA8Itineraries,
[ArchV7A, FeatureThumb2, FeatureNEON, FeatureHasSlowVMLx, [ArchV7A, FeatureThumb2, FeatureNEON, FeatureHasSlowVMLx,
FeatureNEONForFP]>; FeatureNEONForFP, FeatureT2ExtractPack]>;
def : Processor<"cortex-a9", CortexA9Itineraries, def : Processor<"cortex-a9", CortexA9Itineraries,
[ArchV7A, FeatureThumb2, FeatureNEON]>; [ArchV7A, FeatureThumb2, FeatureNEON, FeatureT2ExtractPack]>;
def : ProcNoItin<"cortex-m3", [ArchV7M, FeatureThumb2]>; def : ProcNoItin<"cortex-m3", [ArchV7M, FeatureThumb2, FeatureHWDiv]>;
def : ProcNoItin<"cortex-m4", [ArchV7M, FeatureThumb2, FeatureHWDiv]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Register File Description // Register File Description

5
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -363,7 +363,7 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
setOperationAction(ISD::BSWAP, MVT::i32, Expand); setOperationAction(ISD::BSWAP, MVT::i32, Expand);
// These are expanded into libcalls. // These are expanded into libcalls.
if (!Subtarget->hasV7MOps()) { if (!Subtarget->hasDivide()) {
// v7M has a hardware divider // v7M has a hardware divider
setOperationAction(ISD::SDIV, MVT::i32, Expand); setOperationAction(ISD::SDIV, MVT::i32, Expand);
setOperationAction(ISD::UDIV, MVT::i32, Expand); setOperationAction(ISD::UDIV, MVT::i32, Expand);
@ -393,7 +393,8 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom); setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
if (!Subtarget->hasV6Ops() && !Subtarget->isThumb2() || Subtarget->hasV7MOps()) { if (!Subtarget->hasV6Ops() && (!Subtarget->isThumb2()
|| !Subtarget->hasT2ExtractPack())) {
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
} }

5
lib/Target/ARM/ARMInstrInfo.td
View File

@ -124,13 +124,12 @@ def HasV6 : Predicate<"Subtarget->hasV6Ops()">;
def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">; def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">;
def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">; def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
def HasV7 : Predicate<"Subtarget->hasV7Ops()">; def HasV7 : Predicate<"Subtarget->hasV7Ops()">;
def HasV7A : Predicate<"Subtarget->hasV7AOps()">;
def HasV7M : Predicate<"Subtarget->hasV7MOps()">;
def NoV7M : Predicate<"!Subtarget->hasV7MOps()">;
def NoVFP : Predicate<"!Subtarget->hasVFP2()">; def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
def HasVFP2 : Predicate<"Subtarget->hasVFP2()">; def HasVFP2 : Predicate<"Subtarget->hasVFP2()">;
def HasVFP3 : Predicate<"Subtarget->hasVFP3()">; def HasVFP3 : Predicate<"Subtarget->hasVFP3()">;
def HasNEON : Predicate<"Subtarget->hasNEON()">; def HasNEON : Predicate<"Subtarget->hasNEON()">;
def HasDivide : Predicate<"Subtarget->hasDivide()">;
def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">;
def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">; def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">; def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
def IsThumb : Predicate<"Subtarget->isThumb()">; def IsThumb : Predicate<"Subtarget->isThumb()">;

28
lib/Target/ARM/ARMInstrThumb2.td
View File

@ -640,7 +640,7 @@ multiclass T2I_unary_rrot<bits<3> opcod, string opc, PatFrag opnode> {
def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr, def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
opc, ".w\t$dst, $src", opc, ".w\t$dst, $src",
[(set GPR:$dst, (opnode GPR:$src))]>, [(set GPR:$dst, (opnode GPR:$src))]>,
Requires<[NoV7M]> { Requires<[HasT2ExtractPack]> {
let Inst{31-27} = 0b11111; let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0100; let Inst{26-23} = 0b0100;
let Inst{22-20} = opcod; let Inst{22-20} = opcod;
@ -652,7 +652,7 @@ multiclass T2I_unary_rrot<bits<3> opcod, string opc, PatFrag opnode> {
def r_rot : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$rot), IIC_iUNAsi, def r_rot : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$rot), IIC_iUNAsi,
opc, ".w\t$dst, $src, ror $rot", opc, ".w\t$dst, $src, ror $rot",
[(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]>, [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]>,
Requires<[NoV7M]> { Requires<[HasT2ExtractPack]> {
let Inst{31-27} = 0b11111; let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0100; let Inst{26-23} = 0b0100;
let Inst{22-20} = opcod; let Inst{22-20} = opcod;
@ -668,7 +668,7 @@ multiclass T2I_unary_rrot_nw<bits<3> opcod, string opc, PatFrag opnode> {
def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr, def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
opc, "\t$dst, $src", opc, "\t$dst, $src",
[(set GPR:$dst, (opnode GPR:$src))]>, [(set GPR:$dst, (opnode GPR:$src))]>,
Requires<[NoV7M]> { Requires<[HasT2ExtractPack]> {
let Inst{31-27} = 0b11111; let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0100; let Inst{26-23} = 0b0100;
let Inst{22-20} = opcod; let Inst{22-20} = opcod;
@ -680,7 +680,7 @@ multiclass T2I_unary_rrot_nw<bits<3> opcod, string opc, PatFrag opnode> {
def r_rot : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$rot), IIC_iUNAsi, def r_rot : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$rot), IIC_iUNAsi,
opc, "\t$dst, $src, ror $rot", opc, "\t$dst, $src, ror $rot",
[(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]>, [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]>,
Requires<[NoV7M]> { Requires<[HasT2ExtractPack]> {
let Inst{31-27} = 0b11111; let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0100; let Inst{26-23} = 0b0100;
let Inst{22-20} = opcod; let Inst{22-20} = opcod;
@ -722,7 +722,7 @@ multiclass T2I_bin_rrot<bits<3> opcod, string opc, PatFrag opnode> {
def rr : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS), IIC_iALUr, def rr : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS), IIC_iALUr,
opc, "\t$dst, $LHS, $RHS", opc, "\t$dst, $LHS, $RHS",
[(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>, [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
Requires<[NoV7M]> { Requires<[HasT2ExtractPack]> {
let Inst{31-27} = 0b11111; let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0100; let Inst{26-23} = 0b0100;
let Inst{22-20} = opcod; let Inst{22-20} = opcod;
@ -734,7 +734,7 @@ multiclass T2I_bin_rrot<bits<3> opcod, string opc, PatFrag opnode> {
IIC_iALUsr, opc, "\t$dst, $LHS, $RHS, ror $rot", IIC_iALUsr, opc, "\t$dst, $LHS, $RHS, ror $rot",
[(set GPR:$dst, (opnode GPR:$LHS, [(set GPR:$dst, (opnode GPR:$LHS,
(rotr GPR:$RHS, rot_imm:$rot)))]>, (rotr GPR:$RHS, rot_imm:$rot)))]>,
Requires<[NoV7M]> { Requires<[HasT2ExtractPack]> {
let Inst{31-27} = 0b11111; let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0100; let Inst{26-23} = 0b0100;
let Inst{22-20} = opcod; let Inst{22-20} = opcod;
@ -866,7 +866,7 @@ def t2SUBrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
def t2SDIV : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iALUi, def t2SDIV : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iALUi,
"sdiv", "\t$dst, $a, $b", "sdiv", "\t$dst, $a, $b",
[(set GPR:$dst, (sdiv GPR:$a, GPR:$b))]>, [(set GPR:$dst, (sdiv GPR:$a, GPR:$b))]>,
Requires<[HasV7M]> { Requires<[HasDivide]> {
let Inst{31-27} = 0b11111; let Inst{31-27} = 0b11111;
let Inst{26-21} = 0b011100; let Inst{26-21} = 0b011100;
let Inst{20} = 0b1; let Inst{20} = 0b1;
@ -877,7 +877,7 @@ def t2SDIV : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iALUi,
def t2UDIV : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iALUi, def t2UDIV : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iALUi,
"udiv", "\t$dst, $a, $b", "udiv", "\t$dst, $a, $b",
[(set GPR:$dst, (udiv GPR:$a, GPR:$b))]>, [(set GPR:$dst, (udiv GPR:$a, GPR:$b))]>,
Requires<[HasV7M]> { Requires<[HasDivide]> {
let Inst{31-27} = 0b11111; let Inst{31-27} = 0b11111;
let Inst{26-21} = 0b011101; let Inst{26-21} = 0b011101;
let Inst{20} = 0b1; let Inst{20} = 0b1;
@ -2069,7 +2069,7 @@ def t2PKHBT : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
[(set GPR:$dst, (or (and GPR:$src1, 0xFFFF), [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
(and (shl GPR:$src2, (i32 imm:$shamt)), (and (shl GPR:$src2, (i32 imm:$shamt)),
0xFFFF0000)))]>, 0xFFFF0000)))]>,
Requires<[NoV7M]> { Requires<[HasT2ExtractPack]> {
let Inst{31-27} = 0b11101; let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01; let Inst{26-25} = 0b01;
let Inst{24-20} = 0b01100; let Inst{24-20} = 0b01100;
@ -2080,17 +2080,17 @@ def t2PKHBT : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
// Alternate cases for PKHBT where identities eliminate some nodes. // Alternate cases for PKHBT where identities eliminate some nodes.
def : T2Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)), def : T2Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
(t2PKHBT GPR:$src1, GPR:$src2, 0)>, (t2PKHBT GPR:$src1, GPR:$src2, 0)>,
Requires<[NoV7M]>; Requires<[HasT2ExtractPack]>;
def : T2Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)), def : T2Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
(t2PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>, (t2PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>,
Requires<[NoV7M]>; Requires<[HasT2ExtractPack]>;
def t2PKHTB : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt), def t2PKHTB : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2, asr $shamt", IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2, asr $shamt",
[(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000), [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
(and (sra GPR:$src2, imm16_31:$shamt), (and (sra GPR:$src2, imm16_31:$shamt),
0xFFFF)))]>, 0xFFFF)))]>,
Requires<[NoV7M]> { Requires<[HasT2ExtractPack]> {
let Inst{31-27} = 0b11101; let Inst{31-27} = 0b11101;
let Inst{26-25} = 0b01; let Inst{26-25} = 0b01;
let Inst{24-20} = 0b01100; let Inst{24-20} = 0b01100;
@ -2102,11 +2102,11 @@ def t2PKHTB : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
// a shift amount of 0 is *not legal* here, it is PKHBT instead. // a shift amount of 0 is *not legal* here, it is PKHBT instead.
def : T2Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))), def : T2Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
(t2PKHTB GPR:$src1, GPR:$src2, 16)>, (t2PKHTB GPR:$src1, GPR:$src2, 16)>,
Requires<[NoV7M]>; Requires<[HasT2ExtractPack]>;
def : T2Pat<(or (and GPR:$src1, 0xFFFF0000), def : T2Pat<(or (and GPR:$src1, 0xFFFF0000),
(and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)), (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
(t2PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>, (t2PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>,
Requires<[NoV7M]>; Requires<[HasT2ExtractPack]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Comparison Instructions... // Comparison Instructions...

2
lib/Target/ARM/ARMSubtarget.cpp
View File

@ -39,6 +39,8 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &FS,
, IsR9Reserved(ReserveR9) , IsR9Reserved(ReserveR9)
, UseMovt(UseMOVT) , UseMovt(UseMOVT)
, HasFP16(false) , HasFP16(false)
, HasHardwareDivide(false)
, HasT2ExtractPack(false)
, stackAlignment(4) , stackAlignment(4)
, CPUString("generic") , CPUString("generic")
, TargetType(isELF) // Default to ELF unless otherwise specified. , TargetType(isELF) // Default to ELF unless otherwise specified.

11
lib/Target/ARM/ARMSubtarget.h
View File

@ -74,6 +74,13 @@ protected:
/// only so far) /// only so far)
bool HasFP16; bool HasFP16;
/// HasHardwareDivide - True if subtarget supports [su]div
bool HasHardwareDivide;
/// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
/// instructions.
bool HasT2ExtractPack;
/// stackAlignment - The minimum alignment known to hold of the stack frame on /// stackAlignment - The minimum alignment known to hold of the stack frame on
/// entry to the function and which must be maintained by every function. /// entry to the function and which must be maintained by every function.
unsigned stackAlignment; unsigned stackAlignment;
@ -117,14 +124,14 @@ protected:
bool hasV6Ops() const { return ARMArchVersion >= V6; } bool hasV6Ops() const { return ARMArchVersion >= V6; }
bool hasV6T2Ops() const { return ARMArchVersion >= V6T2; } bool hasV6T2Ops() const { return ARMArchVersion >= V6T2; }
bool hasV7Ops() const { return ARMArchVersion >= V7A; } bool hasV7Ops() const { return ARMArchVersion >= V7A; }
bool hasV7AOps() const { return ARMArchVersion == V7A; }
bool hasV7MOps() const { return ARMArchVersion == V7M; }
bool hasVFP2() const { return ARMFPUType >= VFPv2; } bool hasVFP2() const { return ARMFPUType >= VFPv2; }
bool hasVFP3() const { return ARMFPUType >= VFPv3; } bool hasVFP3() const { return ARMFPUType >= VFPv3; }
bool hasNEON() const { return ARMFPUType >= NEON; } bool hasNEON() const { return ARMFPUType >= NEON; }
bool useNEONForSinglePrecisionFP() const { bool useNEONForSinglePrecisionFP() const {
return hasNEON() && UseNEONForSinglePrecisionFP; } return hasNEON() && UseNEONForSinglePrecisionFP; }
bool hasDivide() const { return HasHardwareDivide; };
bool hasT2ExtractPack() const { return HasT2ExtractPack; };
bool useVMLx() const {return hasVFP2() && !SlowVMLx; } bool useVMLx() const {return hasVFP2() && !SlowVMLx; }
bool hasFP16() const { return HasFP16; } bool hasFP16() const { return HasFP16; }

4
test/CodeGen/Thumb2/thumb2-pack.ll
View File

@ -1,6 +1,6 @@
; RUN: llc < %s -march=thumb -mattr=+thumb2 | \ ; RUN: llc < %s -march=thumb -mattr=+thumb2,+t2xtpk | \
; RUN: grep pkhbt | count 5 ; RUN: grep pkhbt | count 5
; RUN: llc < %s -march=thumb -mattr=+thumb2 | \ ; RUN: llc < %s -march=thumb -mattr=+thumb2,+t2xtpk | \
; RUN: grep pkhtb | count 4 ; RUN: grep pkhtb | count 4
define i32 @test1(i32 %X, i32 %Y) { define i32 @test1(i32 %X, i32 %Y) {

2
test/CodeGen/Thumb2/thumb2-rev.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=thumb -mattr=+thumb2,+v7a | FileCheck %s ; RUN: llc < %s -march=thumb -mattr=+thumb2,+v7a,+t2xtpk | FileCheck %s
define i32 @f1(i32 %a) { define i32 @f1(i32 %a) {
; CHECK: f1: ; CHECK: f1:

2
test/CodeGen/Thumb2/thumb2-shifter.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s ; RUN: llc < %s -march=thumb -mattr=+thumb2,+t2xtpk | FileCheck %s
define i32 @t2ADDrs_lsl(i32 %X, i32 %Y) { define i32 @t2ADDrs_lsl(i32 %X, i32 %Y) {
; CHECK: t2ADDrs_lsl ; CHECK: t2ADDrs_lsl

2
test/CodeGen/Thumb2/thumb2-smla.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s ; RUN: llc < %s -march=thumb -mattr=+thumb2,+t2xtpk | FileCheck %s
define i32 @f3(i32 %a, i16 %x, i32 %y) { define i32 @f3(i32 %a, i16 %x, i32 %y) {
; CHECK: f3 ; CHECK: f3

2
test/CodeGen/Thumb2/thumb2-smul.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s ; RUN: llc < %s -march=thumb -mattr=+thumb2,+t2xtpk | FileCheck %s
@x = weak global i16 0 ; <i16*> [#uses=1] @x = weak global i16 0 ; <i16*> [#uses=1]
@y = weak global i16 0 ; <i16*> [#uses=0] @y = weak global i16 0 ; <i16*> [#uses=0]

2
test/CodeGen/Thumb2/thumb2-sxt_rot.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s ; RUN: llc < %s -march=thumb -mattr=+thumb2,+t2xtpk | FileCheck %s
define i32 @test0(i8 %A) { define i32 @test0(i8 %A) {
; CHECK: test0 ; CHECK: test0

2
test/CodeGen/Thumb2/thumb2-uxt_rot.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s ; RUN: llc < %s -march=thumb -mattr=+thumb2,+t2xtpk | FileCheck %s
define i8 @test1(i32 %A.u) zeroext { define i8 @test1(i32 %A.u) zeroext {
; CHECK: test1 ; CHECK: test1

2
test/CodeGen/Thumb2/thumb2-uxtb.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s ; RUN: llc < %s -march=thumb -mattr=+thumb2,+t2xtpk | FileCheck %s
define i32 @test1(i32 %x) { define i32 @test1(i32 %x) {
; CHECK: test1 ; CHECK: test1