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https://github.com/RPCS3/llvm.git
synced 2025-01-26 04:34:41 +00:00
Revert 298388 and 298389 because they broke some AMDGPU tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298401 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Adrian Prantl
parent
32a326f95b
commit
2a9589584e
@ -98,7 +98,7 @@ bool DwarfExpression::addMachineReg(const TargetRegisterInfo &TRI,
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// If this is a valid register number, emit it.
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if (Reg >= 0) {
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DwarfRegs.push_back({Reg, 0, nullptr});
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addReg(Reg);
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return true;
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}
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@ -110,7 +110,7 @@ bool DwarfExpression::addMachineReg(const TargetRegisterInfo &TRI,
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unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg);
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unsigned Size = TRI.getSubRegIdxSize(Idx);
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unsigned RegOffset = TRI.getSubRegIdxOffset(Idx);
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DwarfRegs.push_back({Reg, 0, "super-register"});
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addReg(Reg, "super-register");
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// Use a DW_OP_bit_piece to describe the sub-register.
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setSubRegisterPiece(Size, RegOffset);
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return true;
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@ -140,17 +140,17 @@ bool DwarfExpression::addMachineReg(const TargetRegisterInfo &TRI,
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// If this sub-register has a DWARF number and we haven't covered
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// its range, emit a DWARF piece for it.
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if (Reg >= 0 && Intersection.any()) {
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// Emit a piece for any gap in the coverage.
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if (Offset > CurPos)
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DwarfRegs.push_back({-1, Offset - CurPos, "missing"});
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DwarfRegs.push_back(
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{Reg, std::min<unsigned>(Size, MaxSize - Offset), "sub-register"});
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addReg(Reg, "sub-register");
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if (Offset >= MaxSize)
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break;
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// emit a piece for the any gap in the coverage.
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if (Offset > CurPos)
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addOpPiece(Offset - CurPos);
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addOpPiece(std::min<unsigned>(Size, MaxSize - Offset));
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CurPos = Offset + Size;
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// Mark it as emitted.
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Coverage.set(Offset, Offset + Size);
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CurPos = Offset + Size;
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}
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}
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@ -194,42 +194,18 @@ bool DwarfExpression::addMachineRegExpression(const TargetRegisterInfo &TRI,
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DIExpressionCursor &ExprCursor,
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unsigned MachineReg,
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unsigned FragmentOffsetInBits) {
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auto Fragment = ExprCursor.getFragmentInfo();
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if (!addMachineReg(TRI, MachineReg, Fragment ? Fragment->SizeInBits : ~1U))
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return false;
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bool HasComplexExpression = false;
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auto Op = ExprCursor.peek();
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if (Op && Op->getOp() != dwarf::DW_OP_LLVM_fragment)
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HasComplexExpression = true;
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// If the register can only be described by a complex expression (i.e.,
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// multiple subregisters) it doesn't safely compose with another complex
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// expression. For example, it is not possible to apply a DW_OP_deref
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// operation to multiple DW_OP_pieces.
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if (HasComplexExpression && DwarfRegs.size() > 1) {
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DwarfRegs.clear();
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return false;
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}
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if (!HasComplexExpression) {
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for (auto &Reg : DwarfRegs) {
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if (Reg.DwarfRegNo >= 0)
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addReg(Reg.DwarfRegNo, Reg.Comment);
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addOpPiece(Reg.Size);
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}
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DwarfRegs.clear();
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return true;
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}
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if (!ExprCursor)
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return addMachineReg(TRI, MachineReg);
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// Pattern-match combinations for which more efficient representations exist
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// first.
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assert(DwarfRegs.size() == 1);
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auto Reg = DwarfRegs[0];
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assert(Reg.Size == 0 && "subregister has same size as superregister");
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bool ValidReg = false;
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auto Op = ExprCursor.peek();
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switch (Op->getOp()) {
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default: {
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addReg(Reg.DwarfRegNo, 0);
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auto Fragment = ExprCursor.getFragmentInfo();
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ValidReg = addMachineReg(TRI, MachineReg,
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Fragment ? Fragment->SizeInBits : ~1U);
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break;
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}
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case dwarf::DW_OP_plus:
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@ -238,28 +214,22 @@ bool DwarfExpression::addMachineRegExpression(const TargetRegisterInfo &TRI,
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// [DW_OP_reg,Offset,DW_OP_minus,DW_OP_deref] --> [DW_OP_breg,-Offset].
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auto N = ExprCursor.peekNext();
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if (N && N->getOp() == dwarf::DW_OP_deref) {
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int Offset = Op->getArg(0);
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int SignedOffset = (Op->getOp() == dwarf::DW_OP_plus) ? Offset : -Offset;
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if (isFrameRegister(TRI, MachineReg)) {
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// If variable offset is based in frame register then use fbreg.
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emitOp(dwarf::DW_OP_fbreg);
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emitSigned(SignedOffset);
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} else
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addRegIndirect(Reg.DwarfRegNo, SignedOffset);
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unsigned Offset = Op->getArg(0);
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ValidReg = addMachineRegIndirect(
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TRI, MachineReg, Op->getOp() == dwarf::DW_OP_plus ? Offset : -Offset);
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ExprCursor.consume(2);
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break;
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}
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addReg(Reg.DwarfRegNo, 0);
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} else
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ValidReg = addMachineReg(TRI, MachineReg);
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break;
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}
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case dwarf::DW_OP_deref:
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// [DW_OP_reg,DW_OP_deref] --> [DW_OP_breg].
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addRegIndirect(Reg.DwarfRegNo, 0);
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ValidReg = addMachineRegIndirect(TRI, MachineReg);
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ExprCursor.take();
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break;
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}
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DwarfRegs.clear();
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return true;
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return ValidReg;
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}
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void DwarfExpression::addExpression(DIExpressionCursor &&ExprCursor,
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@ -338,7 +308,6 @@ void DwarfExpression::maskSubRegister() {
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void DwarfExpression::finalize() {
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assert(DwarfRegs.size() == 0 && "dwarf registers not emitted");
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// Emit any outstanding DW_OP_piece operations to mask out subregisters.
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if (SubRegisterSizeInBits == 0)
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return;
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@ -84,16 +84,6 @@ public:
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/// entry.
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class DwarfExpression {
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protected:
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/// Holds information about all subregisters comprising a register location.
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struct Register {
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int DwarfRegNo;
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unsigned Size;
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const char *Comment;
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};
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/// The register location, if any.
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SmallVector<Register, 2> DwarfRegs;
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/// Current Fragment Offset in Bits.
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uint64_t OffsetInBits = 0;
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unsigned DwarfVersion;
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@ -1,122 +0,0 @@
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# RUN: llc -filetype=obj -o - %s | llvm-dwarfdump - | FileCheck %s
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#
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# This is an artificial example of a debug value residing in a composite
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# location with a complex expression. Because the semantics of applying a DWARF
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# expression to a composite location are ill-defined, the compiler should bail
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# out of emitting a location.
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#
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# CHECK: .debug_info contents:
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# CHECK: DW_TAG_variable
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# CHECK-NOT: DW_AT_location
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# CHECK: DW_TAG
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--- |
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; Generated from:
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; typedef float vec2 __attribute__((vector_size(16)));
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; vec2 v();
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; float f() {
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; vec2 vec = v();
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; return vec[0] + vec[1];
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; }
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target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
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target triple = "thumbv7s-apple-ios5.0.0"
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define float @f() local_unnamed_addr #0 !dbg !9 {
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entry:
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%call = tail call <4 x float> bitcast (<4 x float> (...)* @v to <4 x float> ()*)() #0, !dbg !19
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tail call void @llvm.dbg.value(metadata <4 x float> %call, i64 0, metadata !14, metadata !20), !dbg !21
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%vecext = extractelement <4 x float> %call, i32 0, !dbg !22
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%vecext1 = extractelement <4 x float> %call, i32 1, !dbg !23
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%add = fadd float %vecext, %vecext1, !dbg !24
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ret float %add, !dbg !25
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}
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declare arm_aapcs_vfpcc <4 x float> @v(...) local_unnamed_addr #0
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declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #0
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attributes #0 = { nounwind readnone }
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!llvm.dbg.cu = !{!0}
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!llvm.module.flags = !{!3, !4}
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!llvm.ident = !{!8}
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!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 4.0.0 (trunk 286322) (llvm/trunk 286305)", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2)
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!1 = !DIFile(filename: "v.c", directory: "/")
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!2 = !{}
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!3 = !{i32 2, !"Dwarf Version", i32 2}
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!4 = !{i32 2, !"Debug Info Version", i32 3}
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!8 = !{!"clang version 4.0.0 (trunk 286322) (llvm/trunk 286305)"}
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!9 = distinct !DISubprogram(name: "f", scope: !1, file: !1, line: 3, type: !10, isLocal: false, isDefinition: true, scopeLine: 3, isOptimized: true, unit: !0, variables: !13)
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!10 = !DISubroutineType(types: !11)
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!11 = !{!12}
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!12 = !DIBasicType(name: "float", size: 32, encoding: DW_ATE_float)
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!13 = !{!14}
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!14 = !DILocalVariable(name: "vec", scope: !9, file: !1, line: 4, type: !15)
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!15 = !DIDerivedType(tag: DW_TAG_typedef, name: "vec2", file: !1, line: 1, baseType: !16)
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!16 = !DICompositeType(tag: DW_TAG_array_type, baseType: !12, size: 128, flags: DIFlagVector, elements: !17)
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!17 = !{!18}
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!18 = !DISubrange(count: 4)
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!19 = !DILocation(line: 4, column: 13, scope: !9)
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!20 = !DIExpression(DW_OP_plus, 1, DW_OP_minus, 1)
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!21 = !DILocation(line: 4, column: 7, scope: !9)
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!22 = !DILocation(line: 5, column: 9, scope: !9)
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!23 = !DILocation(line: 5, column: 18, scope: !9)
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!24 = !DILocation(line: 5, column: 16, scope: !9)
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!25 = !DILocation(line: 5, column: 2, scope: !9)
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...
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---
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name: f
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alignment: 1
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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calleeSavedRegisters: [ '%lr', '%d8', '%d9', '%d10', '%d11', '%d12', '%d13',
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'%d14', '%d15', '%q4', '%q5', '%q6', '%q7', '%r4',
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'%r5', '%r6', '%r7', '%r8', '%r10', '%r11', '%s16',
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'%s17', '%s18', '%s19', '%s20', '%s21', '%s22',
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'%s23', '%s24', '%s25', '%s26', '%s27', '%s28',
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'%s29', '%s30', '%s31', '%d8_d10', '%d9_d11', '%d10_d12',
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'%d11_d13', '%d12_d14', '%d13_d15', '%q4_q5', '%q5_q6',
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'%q6_q7', '%q4_q5_q6_q7', '%r4_r5', '%r6_r7', '%r10_r11',
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'%d8_d9_d10', '%d9_d10_d11', '%d10_d11_d12', '%d11_d12_d13',
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'%d12_d13_d14', '%d13_d14_d15', '%d8_d10_d12',
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'%d9_d11_d13', '%d10_d12_d14', '%d11_d13_d15',
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'%d8_d10_d12_d14', '%d9_d11_d13_d15', '%d9_d10',
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'%d11_d12', '%d13_d14', '%d9_d10_d11_d12', '%d11_d12_d13_d14' ]
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 4
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offsetAdjustment: 0
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maxAlignment: 4
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adjustsStack: true
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hasCalls: true
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maxCallFrameSize: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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stack:
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- { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '%lr' }
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body: |
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bb.0.entry:
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liveins: %lr
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early-clobber %sp = frame-setup t2STR_PRE killed undef %lr, %sp, -4, 14, _
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frame-setup CFI_INSTRUCTION def_cfa_offset 4
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frame-setup CFI_INSTRUCTION offset %lr, -4
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tBL 14, _, @v, csr_ios, implicit-def dead %lr, implicit %sp, implicit-def %sp, implicit-def %r0, implicit-def %r1, implicit-def %r2, implicit-def %r3, debug-location !19
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%d1 = VMOVDRR killed %r2, killed %r3, 14, _, implicit-def %q0, debug-location !19
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%d0 = VMOVDRR killed %r0, killed %r1, 14, _, implicit killed %q0, implicit-def %q0, debug-location !19
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DBG_VALUE debug-use %q0, debug-use _, !14, !20, debug-location !21
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%s4 = VMOVS %s1, 14, _, implicit-def %d2, debug-location !24
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%d0 = VADDfd %d0, killed %d2, 14, _, implicit killed %q0, debug-location !24
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%r0 = VMOVRS %s0, 14, _, implicit killed %d0, debug-location !25
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%lr, %sp = t2LDR_POST %sp, 4, 14, _, debug-location !25
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tBX_RET 14, _, implicit %r0, debug-location !25
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...
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