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Annotate control instructions with SchedRW lists.
This could definitely be more granular. I am not sure if it makes a difference. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178049 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
parent
cdf7625960
commit
2bb3fcd490
@ -20,7 +20,7 @@
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// The X86retflag return instructions are variadic because we may add ST0 and
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// ST1 arguments when returning values on the x87 stack.
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let isTerminator = 1, isReturn = 1, isBarrier = 1,
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hasCtrlDep = 1, FPForm = SpecialFP in {
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hasCtrlDep = 1, FPForm = SpecialFP, SchedRW = [WriteJumpLd] in {
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def RET : I <0xC3, RawFrm, (outs), (ins variable_ops),
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"ret",
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[(X86retflag 0)], IIC_RET>;
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@ -46,7 +46,7 @@ let isTerminator = 1, isReturn = 1, isBarrier = 1,
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}
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// Unconditional branches.
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let isBarrier = 1, isBranch = 1, isTerminator = 1 in {
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let isBarrier = 1, isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in {
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def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
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"jmp\t$dst", [(br bb:$dst)], IIC_JMP_REL>;
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def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
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@ -58,7 +58,7 @@ let isBarrier = 1, isBranch = 1, isTerminator = 1 in {
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}
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// Conditional Branches.
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let isBranch = 1, isTerminator = 1, Uses = [EFLAGS] in {
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let isBranch = 1, isTerminator = 1, Uses = [EFLAGS], SchedRW = [WriteJump] in {
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multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
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def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, [],
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IIC_Jcc>;
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@ -85,7 +85,7 @@ defm JLE : ICBr<0x7E, 0x8E, "jle\t$dst", X86_COND_LE>;
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defm JG : ICBr<0x7F, 0x8F, "jg\t$dst" , X86_COND_G>;
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// jcx/jecx/jrcx instructions.
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let isBranch = 1, isTerminator = 1 in {
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let isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in {
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// These are the 32-bit versions of this instruction for the asmparser. In
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// 32-bit mode, the address size prefix is jcxz and the unprefixed version is
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// jecxz.
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@ -110,36 +110,46 @@ let isBranch = 1, isTerminator = 1 in {
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// Indirect branches
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let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
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def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
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[(brind GR32:$dst)], IIC_JMP_REG>, Requires<[In32BitMode]>;
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[(brind GR32:$dst)], IIC_JMP_REG>, Requires<[In32BitMode]>,
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Sched<[WriteJump]>;
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def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
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[(brind (loadi32 addr:$dst))], IIC_JMP_MEM>, Requires<[In32BitMode]>;
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[(brind (loadi32 addr:$dst))], IIC_JMP_MEM>,
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Requires<[In32BitMode]>, Sched<[WriteJumpLd]>;
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def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
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[(brind GR64:$dst)], IIC_JMP_REG>, Requires<[In64BitMode]>;
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[(brind GR64:$dst)], IIC_JMP_REG>, Requires<[In64BitMode]>,
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Sched<[WriteJump]>;
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def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
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[(brind (loadi64 addr:$dst))], IIC_JMP_MEM>, Requires<[In64BitMode]>;
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[(brind (loadi64 addr:$dst))], IIC_JMP_MEM>,
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Requires<[In64BitMode]>, Sched<[WriteJumpLd]>;
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def FARJMP16i : Iseg16<0xEA, RawFrmImm16, (outs),
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(ins i16imm:$off, i16imm:$seg),
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"ljmp{w}\t{$seg, $off|$off, $seg}", [], IIC_JMP_FAR_PTR>, OpSize;
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"ljmp{w}\t{$seg, $off|$off, $seg}", [],
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IIC_JMP_FAR_PTR>, OpSize, Sched<[WriteJump]>;
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def FARJMP32i : Iseg32<0xEA, RawFrmImm16, (outs),
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(ins i32imm:$off, i16imm:$seg),
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"ljmp{l}\t{$seg, $off|$off, $seg}", [], IIC_JMP_FAR_PTR>;
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"ljmp{l}\t{$seg, $off|$off, $seg}", [],
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IIC_JMP_FAR_PTR>, Sched<[WriteJump]>;
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def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst),
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"ljmp{q}\t{*}$dst", [], IIC_JMP_FAR_MEM>;
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"ljmp{q}\t{*}$dst", [], IIC_JMP_FAR_MEM>,
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Sched<[WriteJump]>;
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def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
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"ljmp{w}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize;
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"ljmp{w}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize,
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Sched<[WriteJumpLd]>;
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def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
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"ljmp{l}\t{*}$dst", [], IIC_JMP_FAR_MEM>;
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"ljmp{l}\t{*}$dst", [], IIC_JMP_FAR_MEM>,
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Sched<[WriteJumpLd]>;
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}
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// Loop instructions
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let SchedRW = [WriteJump] in {
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def LOOP : Ii8PCRel<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", [], IIC_LOOP>;
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def LOOPE : Ii8PCRel<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", [], IIC_LOOPE>;
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def LOOPNE : Ii8PCRel<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", [], IIC_LOOPNE>;
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}
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//===----------------------------------------------------------------------===//
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// Call Instructions...
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@ -152,27 +162,31 @@ let isCall = 1 in
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let Uses = [ESP] in {
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def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
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(outs), (ins i32imm_pcrel:$dst),
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"call{l}\t$dst", [], IIC_CALL_RI>, Requires<[In32BitMode]>;
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"call{l}\t$dst", [], IIC_CALL_RI>,
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Requires<[In32BitMode]>, Sched<[WriteJump]>;
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def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst),
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"call{l}\t{*}$dst", [(X86call GR32:$dst)], IIC_CALL_RI>,
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Requires<[In32BitMode]>;
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Requires<[In32BitMode]>, Sched<[WriteJump]>;
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def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst),
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"call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))], IIC_CALL_MEM>,
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Requires<[In32BitMode]>;
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"call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))],
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IIC_CALL_MEM>,
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Requires<[In32BitMode]>, Sched<[WriteJumpLd]>;
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def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs),
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(ins i16imm:$off, i16imm:$seg),
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"lcall{w}\t{$seg, $off|$off, $seg}", [],
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IIC_CALL_FAR_PTR>, OpSize;
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IIC_CALL_FAR_PTR>, OpSize, Sched<[WriteJump]>;
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def FARCALL32i : Iseg32<0x9A, RawFrmImm16, (outs),
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(ins i32imm:$off, i16imm:$seg),
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"lcall{l}\t{$seg, $off|$off, $seg}", [],
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IIC_CALL_FAR_PTR>;
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IIC_CALL_FAR_PTR>, Sched<[WriteJump]>;
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def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
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"lcall{w}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize;
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"lcall{w}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize,
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Sched<[WriteJumpLd]>;
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def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
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"lcall{l}\t{*}$dst", [], IIC_CALL_FAR_MEM>;
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"lcall{l}\t{*}$dst", [], IIC_CALL_FAR_MEM>,
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Sched<[WriteJumpLd]>;
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// callw for 16 bit code for the assembler.
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let isAsmParserOnly = 1 in
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@ -185,7 +199,7 @@ let isCall = 1 in
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// Tail call stuff.
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let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
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isCodeGenOnly = 1 in
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isCodeGenOnly = 1, SchedRW = [WriteJumpLd] in
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let Uses = [ESP] in {
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def TCRETURNdi : PseudoI<(outs),
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(ins i32imm_pcrel:$dst, i32imm:$offset), []>;
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@ -216,7 +230,7 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
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// RSP is marked as a use to prevent stack-pointer assignments that appear
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// immediately before calls from potentially appearing dead. Uses for argument
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// registers are added manually.
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let isCall = 1, Uses = [RSP] in {
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let isCall = 1, Uses = [RSP], SchedRW = [WriteJump] in {
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// NOTE: this pattern doesn't match "X86call imm", because we do not know
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// that the offset between an arbitrary immediate and the call will fit in
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// the 32-bit pcrel field that we have.
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@ -245,13 +259,12 @@ let isCall = 1, isCodeGenOnly = 1 in
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def W64ALLOCA : Ii32PCRel<0xE8, RawFrm,
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(outs), (ins i64i32imm_pcrel:$dst),
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"call{q}\t$dst", [], IIC_CALL_RI>,
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Requires<[IsWin64]>;
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Requires<[IsWin64]>, Sched<[WriteJump]>;
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}
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let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
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isCodeGenOnly = 1 in
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let Uses = [RSP],
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usesCustomInserter = 1 in {
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isCodeGenOnly = 1, Uses = [RSP], usesCustomInserter = 1,
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SchedRW = [WriteJump] in {
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def TCRETURNdi64 : PseudoI<(outs),
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(ins i64i32imm_pcrel:$dst, i32imm:$offset),
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[]>;
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