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R600/SI: Add enums for some hard-coded values
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218250 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -375,13 +375,17 @@ SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
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SDLoc SL, SDValue Chain,
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unsigned Offset, bool Signed) const {
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const DataLayout *DL = getDataLayout();
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MachineFunction &MF = DAG.getMachineFunction();
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const SIRegisterInfo *TRI =
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static_cast<const SIRegisterInfo*>(Subtarget->getRegisterInfo());
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unsigned InputPtrReg = TRI->getPreloadedValue(MF, SIRegisterInfo::INPUT_PTR);
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Type *Ty = VT.getTypeForEVT(*DAG.getContext());
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MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
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PointerType *PtrTy = PointerType::get(Ty, AMDGPUAS::CONSTANT_ADDRESS);
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SDValue BasePtr = DAG.getCopyFromReg(Chain, SL,
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MRI.getLiveInVirtReg(AMDGPU::SGPR0_SGPR1), MVT::i64);
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MRI.getLiveInVirtReg(InputPtrReg), MVT::i64);
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SDValue Ptr = DAG.getNode(ISD::ADD, SL, MVT::i64, BasePtr,
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DAG.getConstant(Offset, MVT::i64));
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SDValue PtrOffset = DAG.getUNDEF(getPointerTy(AMDGPUAS::CONSTANT_ADDRESS));
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@ -403,8 +407,9 @@ SDValue SITargetLowering::LowerFormalArguments(
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SDLoc DL, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const {
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const TargetRegisterInfo *TRI =
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getTargetMachine().getSubtargetImpl()->getRegisterInfo();
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const TargetMachine &TM = getTargetMachine();
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const SIRegisterInfo *TRI =
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static_cast<const SIRegisterInfo*>(TM.getSubtargetImpl()->getRegisterInfo());
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MachineFunction &MF = DAG.getMachineFunction();
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FunctionType *FType = MF.getFunction()->getFunctionType();
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@ -472,12 +477,27 @@ SDValue SITargetLowering::LowerFormalArguments(
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// The pointer to the scratch buffer is stored in SGPR2, SGPR3
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if (Info->getShaderType() == ShaderType::COMPUTE) {
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Info->NumUserSGPRs = 4;
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CCInfo.AllocateReg(AMDGPU::SGPR0);
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CCInfo.AllocateReg(AMDGPU::SGPR1);
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CCInfo.AllocateReg(AMDGPU::SGPR2);
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CCInfo.AllocateReg(AMDGPU::SGPR3);
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MF.addLiveIn(AMDGPU::SGPR0_SGPR1, &AMDGPU::SReg_64RegClass);
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MF.addLiveIn(AMDGPU::SGPR2_SGPR3, &AMDGPU::SReg_64RegClass);
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unsigned InputPtrReg =
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TRI->getPreloadedValue(MF, SIRegisterInfo::INPUT_PTR);
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unsigned InputPtrRegLo =
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TRI->getPhysRegSubReg(InputPtrReg, &AMDGPU::SReg_32RegClass, 0);
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unsigned InputPtrRegHi =
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TRI->getPhysRegSubReg(InputPtrReg, &AMDGPU::SReg_32RegClass, 1);
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unsigned ScratchPtrReg =
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TRI->getPreloadedValue(MF, SIRegisterInfo::SCRATCH_PTR);
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unsigned ScratchPtrRegLo =
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TRI->getPhysRegSubReg(ScratchPtrReg, &AMDGPU::SReg_32RegClass, 0);
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unsigned ScratchPtrRegHi =
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TRI->getPhysRegSubReg(ScratchPtrReg, &AMDGPU::SReg_32RegClass, 1);
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CCInfo.AllocateReg(InputPtrRegLo);
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CCInfo.AllocateReg(InputPtrRegHi);
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CCInfo.AllocateReg(ScratchPtrRegLo);
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CCInfo.AllocateReg(ScratchPtrRegHi);
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MF.addLiveIn(InputPtrReg, &AMDGPU::SReg_64RegClass);
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MF.addLiveIn(ScratchPtrReg, &AMDGPU::SReg_64RegClass);
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}
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if (Info->getShaderType() == ShaderType::COMPUTE) {
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@ -874,7 +894,8 @@ SDValue SITargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI,
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SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
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SelectionDAG &DAG) const {
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MachineFunction &MF = DAG.getMachineFunction();
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SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
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const SIRegisterInfo *TRI =
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static_cast<const SIRegisterInfo*>(MF.getSubtarget().getRegisterInfo());
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EVT VT = Op.getValueType();
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SDLoc DL(Op);
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@ -882,41 +903,50 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
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switch (IntrinsicID) {
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case Intrinsic::r600_read_ngroups_x:
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return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 0, false);
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return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
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SI::KernelInputOffsets::NGROUPS_X, false);
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case Intrinsic::r600_read_ngroups_y:
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return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 4, false);
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return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
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SI::KernelInputOffsets::NGROUPS_Y, false);
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case Intrinsic::r600_read_ngroups_z:
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return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 8, false);
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return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
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SI::KernelInputOffsets::NGROUPS_Z, false);
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case Intrinsic::r600_read_global_size_x:
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return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 12, false);
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return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
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SI::KernelInputOffsets::GLOBAL_SIZE_X, false);
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case Intrinsic::r600_read_global_size_y:
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return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 16, false);
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return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
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SI::KernelInputOffsets::GLOBAL_SIZE_Y, false);
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case Intrinsic::r600_read_global_size_z:
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return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 20, false);
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return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
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SI::KernelInputOffsets::GLOBAL_SIZE_Z, false);
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case Intrinsic::r600_read_local_size_x:
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return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 24, false);
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return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
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SI::KernelInputOffsets::LOCAL_SIZE_X, false);
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case Intrinsic::r600_read_local_size_y:
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return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 28, false);
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return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
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SI::KernelInputOffsets::LOCAL_SIZE_Y, false);
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case Intrinsic::r600_read_local_size_z:
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return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(), 32, false);
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return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
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SI::KernelInputOffsets::LOCAL_SIZE_Z, false);
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case Intrinsic::r600_read_tgid_x:
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return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
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AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 0), VT);
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TRI->getPreloadedValue(MF, SIRegisterInfo::TGID_X), VT);
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case Intrinsic::r600_read_tgid_y:
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return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
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AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 1), VT);
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TRI->getPreloadedValue(MF, SIRegisterInfo::TGID_Y), VT);
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case Intrinsic::r600_read_tgid_z:
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return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
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AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 2), VT);
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TRI->getPreloadedValue(MF, SIRegisterInfo::TGID_Z), VT);
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case Intrinsic::r600_read_tidig_x:
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return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
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AMDGPU::VGPR0, VT);
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TRI->getPreloadedValue(MF, SIRegisterInfo::TIDIG_X), VT);
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case Intrinsic::r600_read_tidig_y:
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return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
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AMDGPU::VGPR1, VT);
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TRI->getPreloadedValue(MF, SIRegisterInfo::TIDIG_Y), VT);
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case Intrinsic::r600_read_tidig_z:
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return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
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AMDGPU::VGPR2, VT);
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TRI->getPreloadedValue(MF, SIRegisterInfo::TIDIG_Z), VT);
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case AMDGPUIntrinsic::SI_load_const: {
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SDValue Ops[] = {
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Op.getOperand(1),
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@ -233,6 +233,25 @@ namespace AMDGPU {
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} // End namespace AMDGPU
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namespace SI {
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namespace KernelInputOffsets {
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/// Offsets in bytes from the start of the input buffer
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enum Offsets {
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NGROUPS_X = 0,
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NGROUPS_Y = 4,
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NGROUPS_Z = 8,
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GLOBAL_SIZE_X = 12,
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GLOBAL_SIZE_Y = 16,
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GLOBAL_SIZE_Z = 20,
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LOCAL_SIZE_X = 24,
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LOCAL_SIZE_Y = 28,
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LOCAL_SIZE_Z = 32
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};
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} // End namespace KernelInputOffsets
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} // End namespace SI
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} // End namespace llvm
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namespace SIInstrFlags {
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@ -306,6 +306,14 @@ unsigned SIRegisterInfo::getPreloadedValue(const MachineFunction &MF,
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return AMDGPU::SReg_32RegClass.getRegister(MFI->NumUserSGPRs + 4);
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case SIRegisterInfo::SCRATCH_PTR:
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return AMDGPU::SGPR2_SGPR3;
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case SIRegisterInfo::INPUT_PTR:
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return AMDGPU::SGPR0_SGPR1;
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case SIRegisterInfo::TIDIG_X:
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return AMDGPU::VGPR0;
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case SIRegisterInfo::TIDIG_Y:
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return AMDGPU::VGPR1;
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case SIRegisterInfo::TIDIG_Z:
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return AMDGPU::VGPR2;
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}
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llvm_unreachable("unexpected preloaded value type");
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}
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@ -80,7 +80,11 @@ struct SIRegisterInfo : public AMDGPURegisterInfo {
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TGID_Y,
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TGID_Z,
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SCRATCH_WAVE_OFFSET,
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SCRATCH_PTR
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SCRATCH_PTR,
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INPUT_PTR,
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TIDIG_X,
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TIDIG_Y,
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TIDIG_Z
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};
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/// \brief Returns the physical register that \p Value is stored in.
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