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Remove redundant writeback flag in ARM addressing mode 5.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98648 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2010-03-16 18:38:09 +00:00
parent ab3460519e
commit 2d357f6b44
6 changed files with 14 additions and 23 deletions
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16
lib/Target/ARM/ARMAddressingModes.h
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@ -484,9 +484,9 @@ namespace ARM_AM {
// operation in bit 8 and the immediate in bits 0-7.
//
// This is also used for FP load/store multiple ops. The second operand
// encodes the writeback mode in bit 8 and the number of registers (or 2
// times the number of registers for DPR ops) in bits 0-7. In addition,
// bits 9-11 encode one of the following two sub-modes:
// encodes the number of registers (or 2 times the number of registers
// for DPR ops) in bits 0-7. In addition, bits 8-10 encode one of the
// following two sub-modes:
//
// IA - Increment after
// DB - Decrement before
@ -505,17 +505,13 @@ namespace ARM_AM {
/// getAM5Opc - This function encodes the addrmode5 opc field for VLDM and
/// VSTM instructions.
static inline unsigned getAM5Opc(AMSubMode SubMode, bool WB,
unsigned char Offset) {
static inline unsigned getAM5Opc(AMSubMode SubMode, unsigned char Offset) {
assert((SubMode == ia || SubMode == db) &&
"Illegal addressing mode 5 sub-mode!");
return ((int)SubMode << 9) | ((int)WB << 8) | Offset;
return ((int)SubMode << 8) | Offset;
}
static inline AMSubMode getAM5SubMode(unsigned AM5Opc) {
return (AMSubMode)((AM5Opc >> 9) & 0x7);
}
static inline bool getAM5WBFlag(unsigned AM5Opc) {
return ((AM5Opc >> 8) & 1);
return (AMSubMode)((AM5Opc >> 8) & 0x7);
}
//===--------------------------------------------------------------------===//

2
lib/Target/ARM/ARMCodeEmitter.cpp
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@ -1353,7 +1353,7 @@ void ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(
Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm()));
// Set bit W(21)
if (ARM_AM::getAM5WBFlag(MO.getImm()))
if (IsUpdating)
Binary |= 0x1 << ARMII::W_BitShift;
// First register is encoded in Dd.

8
lib/Target/ARM/ARMInstrVFP.td
View File

@ -94,7 +94,7 @@ def VLDMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dsts,
def VLDMD_UPD : AXDI5<(outs GPR:$wb), (ins addrmode5:$addr, pred:$p,
reglist:$dsts, variable_ops),
IndexModeUpd, IIC_fpLoadm,
"vldm${addr:submode}${p}\t${addr:base}, $dsts",
"vldm${addr:submode}${p}\t${addr:base}!, $dsts",
"$addr.base = $wb", []> {
let Inst{20} = 1;
}
@ -102,7 +102,7 @@ def VLDMD_UPD : AXDI5<(outs GPR:$wb), (ins addrmode5:$addr, pred:$p,
def VLDMS_UPD : AXSI5<(outs GPR:$wb), (ins addrmode5:$addr, pred:$p,
reglist:$dsts, variable_ops),
IndexModeUpd, IIC_fpLoadm,
"vldm${addr:submode}${p}\t${addr:base}, $dsts",
"vldm${addr:submode}${p}\t${addr:base}!, $dsts",
"$addr.base = $wb", []> {
let Inst{20} = 1;
}
@ -124,7 +124,7 @@ def VSTMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$srcs,
def VSTMD_UPD : AXDI5<(outs GPR:$wb), (ins addrmode5:$addr, pred:$p,
reglist:$srcs, variable_ops),
IndexModeUpd, IIC_fpStorem,
"vstm${addr:submode}${p}\t${addr:base}, $srcs",
"vstm${addr:submode}${p}\t${addr:base}!, $srcs",
"$addr.base = $wb", []> {
let Inst{20} = 0;
}
@ -132,7 +132,7 @@ def VSTMD_UPD : AXDI5<(outs GPR:$wb), (ins addrmode5:$addr, pred:$p,
def VSTMS_UPD : AXSI5<(outs GPR:$wb), (ins addrmode5:$addr, pred:$p,
reglist:$srcs, variable_ops),
IndexModeUpd, IIC_fpStorem,
"vstm${addr:submode}${p}\t${addr:base}, $srcs",
"vstm${addr:submode}${p}\t${addr:base}!, $srcs",
"$addr.base = $wb", []> {
let Inst{20} = 0;
}

7
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
View File

@ -253,7 +253,7 @@ ARMLoadStoreOpt::MergeOps(MachineBasicBlock &MBB,
.addImm(ARM_AM::getAM4ModeImm(Mode)).addImm(Pred).addReg(PredReg)
: BuildMI(MBB, MBBI, dl, TII->get(Opcode))
.addReg(Base, getKillRegState(BaseKill))
.addImm(ARM_AM::getAM5Opc(Mode, false, isDPR ? NumRegs<<1 : NumRegs))
.addImm(ARM_AM::getAM5Opc(Mode, isDPR ? NumRegs<<1 : NumRegs))
.addImm(Pred).addReg(PredReg);
for (unsigned i = 0; i != NumRegs; ++i)
MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef)
@ -508,7 +508,6 @@ bool ARMLoadStoreOpt::MergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
Mode = ARM_AM::getAM4SubMode(MI->getOperand(1).getImm());
} else {
// VLDM{D|S}, VSTM{D|S} addressing mode 5 ops.
assert(!ARM_AM::getAM5WBFlag(MI->getOperand(1).getImm()));
Mode = ARM_AM::getAM5SubMode(MI->getOperand(1).getImm());
Offset = ARM_AM::getAM5Offset(MI->getOperand(1).getImm());
}
@ -576,7 +575,7 @@ bool ARMLoadStoreOpt::MergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
.addImm(Pred).addReg(PredReg);
} else {
// VLDM[SD}_UPD, VSTM[SD]_UPD
MIB.addImm(ARM_AM::getAM5Opc(Mode, true, Offset))
MIB.addImm(ARM_AM::getAM5Opc(Mode, Offset))
.addImm(Pred).addReg(PredReg);
}
// Transfer the rest of operands.
@ -708,7 +707,7 @@ bool ARMLoadStoreOpt::MergeBaseUpdateLoadStore(MachineBasicBlock &MBB,
unsigned Offset = 0;
if (isAM5)
Offset = ARM_AM::getAM5Opc(AddSub == ARM_AM::sub ? ARM_AM::db : ARM_AM::ia,
true, (isDPR ? 2 : 1));
(isDPR ? 2 : 1));
else if (isAM2)
Offset = ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift);
else

2
lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
View File

@ -546,8 +546,6 @@ void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
} else if (Modifier && strcmp(Modifier, "base") == 0) {
// Used for FSTM{D|S} and LSTM{D|S} operations.
O << getRegisterName(MO1.getReg());
if (ARM_AM::getAM5WBFlag(MO2.getImm()))
O << "!";
return;
}

2
lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp
View File

@ -252,8 +252,6 @@ void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
} else if (Modifier && strcmp(Modifier, "base") == 0) {
// Used for FSTM{D|S} and LSTM{D|S} operations.
O << getRegisterName(MO1.getReg());
if (ARM_AM::getAM5WBFlag(MO2.getImm()))
O << "!";
return;
}