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add a bunch of aliases for fp operations with no operand,

Browse Source 
rdar://8431422


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113929 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2010-09-15 04:04:33 +00:00
parent 00002796bb
commit 2d592d10a5
2 changed files with 47 additions and 5 deletions
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27
lib/Target/X86/AsmParser/X86AsmParser.cpp
View File

@ -923,6 +923,24 @@ ParseInstruction(StringRef Name, SMLoc NameLoc,
std::swap(Operands[1], Operands[2]);
}
// The assembler accepts these instructions with no operand as a synonym for
// an instruction acting on st(1). e.g. "fxch" -> "fxch %st(1)".
if ((Name == "fxch" || Name == "fucom" || Name == "fucomp" ||
Name == "faddp" || Name == "fsubp" || Name == "fsubrp" ||
Name == "fmulp" || Name == "fdivp" || Name == "fdivrp") &&
Operands.size() == 1) {
Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(1)"),
NameLoc, NameLoc));
}
// The assembler accepts these instructions with no operand as a synonym for
// an instruction acting on st,st(1). e.g. "faddp" -> "faddp %st(0),%st(1)".
//if (() &&
// Operands.size() == 1) {
// Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(1)"),
// NameLoc, NameLoc));
//}
return false;
}
@ -959,11 +977,10 @@ bool X86ATTAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
}
bool
X86ATTAsmParser::MatchInstruction(SMLoc IDLoc,
const SmallVectorImpl<MCParsedAsmOperand*>
&Operands,
MCInst &Inst) {
bool X86ATTAsmParser::
MatchInstruction(SMLoc IDLoc,
const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
MCInst &Inst) {
assert(!Operands.empty() && "Unexpect empty operand list!");
bool WasOriginallyInvalidOperand = false;

25
test/MC/AsmParser/X86/x86_instructions.s
View File

@ -210,3 +210,28 @@ inl %dx
out %al, (%dx)
out %ax, (%dx)
outl %eax, (%dx)
// rdar://8431422
// CHECK: fxch %st(1)
// CHECK: fucom %st(1)
// CHECK: fucomp %st(1)
// CHECK: faddp %st(1)
// CHECK: faddp %st(0)
// CHECK: fsubp %st(1)
// CHECK: fsubrp %st(1)
// CHECK: fmulp %st(1)
// CHECK: fdivp %st(1)
// CHECK: fdivrp %st(1)
fxch
fucom
fucomp
faddp
faddp %st
fsubp
fsubrp
fmulp
fdivp
fdivrp