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R600/SI: Use address space in allowsUnalignedMemoryAccesses

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207126 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2014-04-24 17:08:26 +00:00
parent 45966fa1f1
commit 2dbbd17394
1 changed files with 30 additions and 0 deletions
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30
lib/Target/R600/SIISelLowering.cpp
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@ -223,10 +223,40 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
bool SITargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
unsigned AddrSpace,
bool *IsFast) const {
if (IsFast)
*IsFast = false;
// XXX: This depends on the address space and also we may want to revist
// the alignment values we specify in the DataLayout.
// TODO: I think v3i32 should allow unaligned accesses on CI with DS_READ_B96,
// which isn't a simple VT.
if (!VT.isSimple() || VT == MVT::Other)
return false;
// XXX - CI changes say "Support for unaligned memory accesses" but I don't
// see what for specifically. The wording everywhere else seems to be the
// same.
// 3.6.4 - Operations using pairs of VGPRs (for example: double-floats) have
// no alignment restrictions.
if (AddrSpace == AMDGPUAS::PRIVATE_ADDRESS) {
// Using any pair of GPRs should be the same as any other pair.
if (IsFast)
*IsFast = true;
return VT.bitsGE(MVT::i64);
}
// XXX - The only mention I see of this in the ISA manual is for LDS direct
// reads the "byte address and must be dword aligned". Is it also true for the
// normal loads and stores?
if (AddrSpace == AMDGPUAS::LOCAL_ADDRESS)
return false;
// 8.1.6 - For Dword or larger reads or writes, the two LSBs of the
// byte-address are ignored, thus forcing Dword alignment.
if (IsFast)
*IsFast = true;
return VT.bitsGT(MVT::i32);
}