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Revert r131664 and fix it in instcombine instead. rdar://9467055

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131708 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2011-05-20 00:54:37 +00:00
parent 5a4b3d8c8f
commit 2e6496026f
7 changed files with 31 additions and 33 deletions
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2
lib/Target/ARM/ARMISelLowering.cpp
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@ -1182,7 +1182,7 @@ ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
bool IsSibCall = false;
// Temporarily disable tail calls so things don't break.
if (!EnableARMTailCalls)
if (!EnableARMTailCalls && !Subtarget->supportsTailCall())
isTailCall = false;
if (isTailCall) {
// Check if it's really possible to do a tail call.

3
lib/Target/ARM/ARMSubtarget.cpp
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@ -46,6 +46,7 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &FS,
, PostRAScheduler(false)
, IsR9Reserved(ReserveR9)
, UseMovt(false)
, SupportsTailCall(false)
, HasFP16(false)
, HasD16(false)
, HasHardwareDivide(false)
@ -153,6 +154,8 @@ ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &FS,
else {
IsR9Reserved = ReserveR9 | (ARMArchVersion < V6);
UseMovt = DarwinUseMOVT && hasV6T2Ops();
const Triple &T = getTargetTriple();
SupportsTailCall = T.getOS() == Triple::IOS && !T.isOSVersionLT(5, 0);
}
if (!isThumb() || hasThumb2())

6
lib/Target/ARM/ARMSubtarget.h
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@ -87,6 +87,11 @@ protected:
/// imms (including global addresses).
bool UseMovt;
/// SupportsTailCall - True if the OS supports tail call. The dynamic linker
/// must be able to synthesize call stubs for interworking between ARM and
/// Thumb.
bool SupportsTailCall;
/// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF
/// only so far)
bool HasFP16;
@ -217,6 +222,7 @@ protected:
bool isR9Reserved() const { return IsR9Reserved; }
bool useMovt() const { return UseMovt && hasV6T2Ops(); }
bool supportsTailCall() const { return SupportsTailCall; }
bool allowsUnalignedMem() const { return AllowsUnalignedMem; }

13
lib/Target/X86/X86ISelLowering.cpp
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@ -10939,19 +10939,6 @@ void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
Mask.getBitWidth() - 1);
break;
case ISD::INTRINSIC_WO_CHAIN: {
unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
switch (IntNo) {
default: break;
case Intrinsic::x86_sse42_crc64_8:
case Intrinsic::x86_sse42_crc64_64:
// crc32 with 64-bit destination zeros high 32-bit.
KnownZero |= APInt::getHighBitsSet(64, 32);
break;
}
break;
}
}
}

4
lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
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@ -780,6 +780,10 @@ Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
// TODO: Could compute known zero/one bits based on the input.
break;
}
case Intrinsic::x86_sse42_crc64_8:
case Intrinsic::x86_sse42_crc64_64:
KnownZero = APInt::getHighBitsSet(64, 32);
return 0;
}
}
ComputeMaskedBits(V, DemandedMask, KnownZero, KnownOne, Depth);

19
test/CodeGen/X86/crc64.ll
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@ -1,19 +0,0 @@
; RUN: llc < %s -march=x86-64 -mattr=sse42 | FileCheck %s
; crc32 with 64-bit destination zeros high 32-bit.
; rdar://9467055
define i64 @t() nounwind {
entry:
; CHECK: t:
; CHECK: crc32q
; CHECK-NOT: mov
; CHECK-NEXT: crc32q
%0 = tail call i64 @llvm.x86.sse42.crc64.64(i64 0, i64 4) nounwind
%1 = and i64 %0, 4294967295
%2 = tail call i64 @llvm.x86.sse42.crc64.64(i64 %1, i64 4) nounwind
%3 = and i64 %2, 4294967295
ret i64 %3
}
declare i64 @llvm.x86.sse42.crc64.64(i64, i64) nounwind readnone

17
test/Transforms/InstCombine/x86-crc32-demanded.ll Normal file
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@ -0,0 +1,17 @@
; RUN: opt < %s -instcombine -S | FileCheck %s
; crc32 with 64-bit destination zeros high 32-bit.
; rdar://9467055
define i64 @test() nounwind {
entry:
; CHECK: test
; CHECK: tail call i64 @llvm.x86.sse42.crc64.64
; CHECK-NOT: and
; CHECK: ret
%0 = tail call i64 @llvm.x86.sse42.crc64.64(i64 0, i64 4) nounwind
%1 = and i64 %0, 4294967295
ret i64 %1
}
declare i64 @llvm.x86.sse42.crc64.64(i64, i64) nounwind readnone