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Convert RegisterAllocator interface to opaque pass type, so that users do not

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need to know _anything_ about RegAlloc to use it.  Well in the end maybe.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1681 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2002-02-04 15:54:09 +00:00
parent 59ba109d9d
commit 2f9b28e59a
4 changed files with 55 additions and 31 deletions
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8
include/llvm/CodeGen/RegisterAllocation.h
View File

@ -9,16 +9,12 @@
#include "llvm/Pass.h"
class TargetMachine;
class MethodPass;
//----------------------------------------------------------------------------
// Entry point for register allocation for a module
//----------------------------------------------------------------------------
class RegisterAllocation : public MethodPass {
TargetMachine &Target;
public:
inline RegisterAllocation(TargetMachine &T) : Target(T) {}
bool runOnMethod(Method *M);
};
MethodPass *getRegisterAllocator(TargetMachine &T);
#endif

38
lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
View File

@ -32,21 +32,35 @@ cl::Enum<RegAllocDebugLevel_t> DEBUG_RA("dregalloc", cl::NoFlags,
clEnumValN(RA_DEBUG_Verbose, "v", "enable extra debug output"), 0);
bool RegisterAllocation::runOnMethod(Method *M) {
if (DEBUG_RA)
cerr << "\n******************** Method "<< M->getName()
<< " ********************\n";
//----------------------------------------------------------------------------
// RegisterAllocation pass front end...
//----------------------------------------------------------------------------
namespace {
class RegisterAllocator : public MethodPass {
TargetMachine &Target;
public:
inline RegisterAllocator(TargetMachine &T) : Target(T) {}
MethodLiveVarInfo LVI(M); // Analyze live varaibles
LVI.analyze();
PhyRegAlloc PRA(M, Target, &LVI); // allocate registers
PRA.allocateRegisters();
if (DEBUG_RA) cerr << "\nRegister allocation complete!\n";
return false;
bool runOnMethod(Method *M) {
if (DEBUG_RA)
cerr << "\n******************** Method "<< M->getName()
<< " ********************\n";
MethodLiveVarInfo LVI(M); // Analyze live varaibles
LVI.analyze();
PhyRegAlloc PRA(M, Target, &LVI); // allocate registers
PRA.allocateRegisters();
if (DEBUG_RA) cerr << "\nRegister allocation complete!\n";
return false;
}
};
}
MethodPass *getRegisterAllocator(TargetMachine &T) {
return new RegisterAllocator(T);
}
//----------------------------------------------------------------------------
// Constructor: Init local composite objects and create register classes.

38
lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
View File

@ -32,21 +32,35 @@ cl::Enum<RegAllocDebugLevel_t> DEBUG_RA("dregalloc", cl::NoFlags,
clEnumValN(RA_DEBUG_Verbose, "v", "enable extra debug output"), 0);
bool RegisterAllocation::runOnMethod(Method *M) {
if (DEBUG_RA)
cerr << "\n******************** Method "<< M->getName()
<< " ********************\n";
//----------------------------------------------------------------------------
// RegisterAllocation pass front end...
//----------------------------------------------------------------------------
namespace {
class RegisterAllocator : public MethodPass {
TargetMachine &Target;
public:
inline RegisterAllocator(TargetMachine &T) : Target(T) {}
MethodLiveVarInfo LVI(M); // Analyze live varaibles
LVI.analyze();
PhyRegAlloc PRA(M, Target, &LVI); // allocate registers
PRA.allocateRegisters();
if (DEBUG_RA) cerr << "\nRegister allocation complete!\n";
return false;
bool runOnMethod(Method *M) {
if (DEBUG_RA)
cerr << "\n******************** Method "<< M->getName()
<< " ********************\n";
MethodLiveVarInfo LVI(M); // Analyze live varaibles
LVI.analyze();
PhyRegAlloc PRA(M, Target, &LVI); // allocate registers
PRA.allocateRegisters();
if (DEBUG_RA) cerr << "\nRegister allocation complete!\n";
return false;
}
};
}
MethodPass *getRegisterAllocator(TargetMachine &T) {
return new RegisterAllocator(T);
}
//----------------------------------------------------------------------------
// Constructor: Init local composite objects and create register classes.

2
lib/Target/SparcV9/SparcV9TargetMachine.cpp
View File

@ -260,7 +260,7 @@ void UltraSparc::addPassesToEmitAssembly(PassManager &PM, std::ostream &Out) {
//PM.add(new InstructionScheduling(*this));
PM.add(new RegisterAllocation(*this));
PM.add(getRegisterAllocator(*this));
//PM.add(new OptimizeLeafProcedures());
//PM.add(new DeleteFallThroughBranches());