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[PowerPC] avoid redundant analysis while lowering an immediate; NFC

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This patch reduces compilation time by avoiding redundant analysis while selecting instructions to create an immediate.
If the instruction count required to create the input number without rotate is 2, we do not need further analysis to find a shorter instruction sequence with rotate; rotate + load constant cannot be done by 1 instruction (i.e. getInt64CountDirectnever return 0).
This patch should not change functionality.

Differential Revision: https://reviews.llvm.org/D34986



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307623 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hiroshi Inoue 2017-07-11 05:28:26 +00:00
parent d2c491251a
commit 2ff5ec7b05
1 changed files with 8 additions and 2 deletions
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10
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
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@ -709,7 +709,10 @@ static uint64_t Rot64(uint64_t Imm, unsigned R) {
static unsigned getInt64Count(int64_t Imm) { static unsigned getInt64Count(int64_t Imm) {
unsigned Count = getInt64CountDirect(Imm); unsigned Count = getInt64CountDirect(Imm);
if (Count == 1)
// If the instruction count is 1 or 2, we do not need further analysis
// since rotate + load constant requires at least 2 instructions.
if (Count <= 2)
return Count; return Count;
for (unsigned r = 1; r < 63; ++r) { for (unsigned r = 1; r < 63; ++r) {
@ -819,7 +822,10 @@ static SDNode *getInt64Direct(SelectionDAG *CurDAG, const SDLoc &dl,
static SDNode *getInt64(SelectionDAG *CurDAG, const SDLoc &dl, int64_t Imm) { static SDNode *getInt64(SelectionDAG *CurDAG, const SDLoc &dl, int64_t Imm) {
unsigned Count = getInt64CountDirect(Imm); unsigned Count = getInt64CountDirect(Imm);
if (Count == 1)
// If the instruction count is 1 or 2, we do not need further analysis
// since rotate + load constant requires at least 2 instructions.
if (Count <= 2)
return getInt64Direct(CurDAG, dl, Imm); return getInt64Direct(CurDAG, dl, Imm);
unsigned RMin = 0; unsigned RMin = 0;