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Allow pseudos to have patterns, no functionality change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23988 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -550,10 +550,10 @@ class MDForm_1<bits<6> opcode, bits<3> xo, dag OL, string asmstr,
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//===----------------------------------------------------------------------===//
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def NoItin : InstrItinClass;
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class Pseudo<dag OL, string asmstr>
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class Pseudo<dag OL, string asmstr, list<dag> pattern>
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: I<0, OL, asmstr, NoItin> {
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let PPC64 = 0;
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let VMX = 0;
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let Pattern = pattern;
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let Inst{31-0} = 0;
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}
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@ -147,25 +147,25 @@ def crbitm: Operand<i8> {
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// PowerPC Instruction Definitions.
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// Pseudo-instructions:
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def PHI : Pseudo<(ops variable_ops), "; PHI">;
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def PHI : Pseudo<(ops variable_ops), "; PHI", []>;
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let isLoad = 1 in {
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def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKDOWN">;
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def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKUP">;
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def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKDOWN", []>;
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def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt), "; ADJCALLSTACKUP", []>;
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}
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def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC">;
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def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; %rD = IMPLICIT_DEF_F8">;
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def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; %rD = IMPLICIT_DEF_F4">;
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def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC", []>;
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def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; %rD = IMPLICIT_DEF_F8", []>;
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def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; %rD = IMPLICIT_DEF_F4", []>;
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// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
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// scheduler into a branch sequence.
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let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
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def SELECT_CC_Int : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
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i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
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i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
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def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F,
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i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
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i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
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def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F,
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i32imm:$BROPC), "; SELECT_CC PSEUDO!">;
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i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
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}
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@ -176,12 +176,12 @@ let isTerminator = 1 in {
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}
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let Defs = [LR] in
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def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label">;
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def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label", []>;
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let isBranch = 1, isTerminator = 1 in {
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def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc,
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target:$true, target:$false),
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"; COND_BRANCH">;
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"; COND_BRANCH", []>;
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def B : IForm<18, 0, 0, (ops target:$func), "b $func", BrB>;
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//def BA : IForm<18, 1, 0, (ops target:$func), "ba $func", BrB>;
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def BL : IForm<18, 0, 1, (ops target:$func), "bl $func", BrB>;
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